c127aed| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 39.000s | 1.498ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 39.000s | 732.719us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 49.000s | 478.463us | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 1.150m | 13.438ms | 1 | 1 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 35.000s | 359.051us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 52.000s | 5.510ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 52.000s | 5.898ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 3.600m | 71.698ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 2.317m | 27.958ms | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 48.000s | 226.343us | 1 | 1 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 56.000s | 427.954us | 1 | 1 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 52.000s | 618.992us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 41.000s | 707.287us | 1 | 1 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 39.000s | 474.311us | 1 | 1 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 49.000s | 1.355ms | 1 | 1 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 40.000s | 66.282us | 1 | 1 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 55.000s | 626.436us | 1 | 1 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 48.000s | 226.343us | 1 | 1 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 42.000s | 114.415us | 1 | 1 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 53.000s | 189.208us | 1 | 1 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 52.000s | 618.992us | 1 | 1 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 52.000s | 32.229us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 51.000s | 525.865us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 52.000s | 77.910us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.200m | 2.494ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.133m | 2.091ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 45.000s | 17.259us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.133m | 2.091ms | 1 | 1 | 100.00 |
| rv_dm_csr_rw | 52.000s | 77.910us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 39.000s | 100.221us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 38.000s | 54.603us | 1 | 1 | 100.00 |
| V1 | TOTAL | 26 | 27 | 96.30 | |||
| V2 | idcode | rv_dm_smoke | 39.000s | 1.498ms | 1 | 1 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 52.000s | 689.042us | 1 | 1 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 53.000s | 739.912us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 47.000s | 95.416us | 1 | 1 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 53.000s | 1.154ms | 1 | 1 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 18.233m | 300.000ms | 0 | 1 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 5.283m | 300.000ms | 0 | 1 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 11.733m | 300.000ms | 0 | 1 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 11.033m | 300.000ms | 0 | 1 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 54.000s | 334.178us | 1 | 1 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 48.000s | 4.197ms | 1 | 1 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 58.000s | 514.298us | 1 | 1 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 49.000s | 146.451us | 1 | 1 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 43.000s | 11.489ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 36.000s | 33.653us | 0 | 1 | 0.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 50.000s | 157.363us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 55.000s | 2.019ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_dm_alert_test | 52.000s | 101.534us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 39.000s | 28.693us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 39.000s | 28.693us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.133m | 2.091ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 51.000s | 525.865us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 52.000s | 77.910us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 59.000s | 154.313us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.133m | 2.091ms | 1 | 1 | 100.00 |
| rv_dm_csr_hw_reset | 51.000s | 525.865us | 1 | 1 | 100.00 | ||
| rv_dm_csr_rw | 52.000s | 77.910us | 1 | 1 | 100.00 | ||
| rv_dm_same_csr_outstanding | 59.000s | 154.313us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 12 | 19 | 63.16 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 57.000s | 2.103ms | 1 | 1 | 100.00 |
| rv_dm_tl_intg_err | 1.117m | 7.441ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 1.117m | 7.441ms | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 48.000s | 4.197ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 51.000s | 123.919us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 48.000s | 4.197ms | 1 | 1 | 100.00 |
| rv_dm_debug_disabled | 51.000s | 123.919us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 39.000s | 1.498ms | 1 | 1 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 53.000s | 579.856us | 1 | 1 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 52.000s | 70.917us | 1 | 1 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 52.000s | 70.917us | 1 | 1 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 53.000s | 579.856us | 1 | 1 | 100.00 |
| V2S | TOTAL | 5 | 5 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 48.000s | 143.995us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 47.000s | 32.548us | 1 | 1 | 100.00 | |
| TOTAL | 44 | 53 | 83.02 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test rv_dm_sba_tl_access has 1 failures.
0.rv_dm_sba_tl_access.85390052443917576907098718520721885692524123433412895863283886773188767286195
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.66201716739060193386600534967784282160037334260523489294547328010168059613417
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 1 failures.
0.rv_dm_bad_sba_tl_access.4777562381607773689556894775449319296192427788151626030056355507492897544879
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
0.rv_dm_autoincr_sba_tl_access.105310859732943232158004053160699155261724064818003226326771112076095562441163
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,TRNULLID: NULL pointer dereference. has 1 failures:
0.rv_dm_tap_fsm.50670502885087034695540022564045251862172119847754523774785472514007105523535
Line 92, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, line = 290, pos = 15
Scope: worklib.cip_base_pkg::cip_base_vseq#(rv_dm_regs_ral_pkg::rv_dm_regs_reg_block,rv_dm_env_pkg::rv_dm_env_cfg,rv_dm_env_pkg::rv_dm_env_cov,rv_dm_env_pkg::rv_dm_virtual_sequencer)@23765_4.tl_access_sub
Time: 11488926846 PS + 0
Verilog Stack Trace:
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24980) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tap_fsm_rand_reset.114625771825000911041134185516715991251223166402679240317683943707969523449795
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 33653270 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24980) { a_addr: 'h6981c72c a_data: 'h2594987b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd0 a_opcode: 'h4 a_user: 'h1835a d_param: 'h0 d_source: 'hd0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 33653270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@27018) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_stress_all_with_rand_reset.70349697702720019964895826398994829981823512824372637667573591808528390258506
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 143994994 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@27018) { a_addr: 'h890d677c a_data: 'he7402486 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h64 a_opcode: 'h4 a_user: 'h182aa d_param: 'h0 d_source: 'h64 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 143994994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@27731) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_tl_errors.35043823610362837842115515042753118101181667162264117088354004840114773350861
Line 86, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 28692771 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@27731) { a_addr: 'h875de5c8 a_data: 'h6a9aa2f1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5e a_opcode: 'h4 a_user: 'h1bcc3 d_param: 'h0 d_source: 'h5e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 28692771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23702) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
0.rv_dm_csr_mem_rw_with_rand_reset.100433519495806308091491219797707492335653861866899288183054189129630534626873
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 17259110 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23702) { a_addr: 'hb5023574 a_data: 'h89d42175 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h79 a_opcode: 'h4 a_user: 'h1a13e d_param: 'h0 d_source: 'h79 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 17259110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---