RV_TIMER Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 8.000s 1.838us 0 1 0.00
V1 csr_hw_reset rv_timer_csr_hw_reset 2.000s 14.434us 1 1 100.00
V1 csr_rw rv_timer_csr_rw 3.000s 31.995us 1 1 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 4.000s 102.699us 1 1 100.00
V1 csr_aliasing rv_timer_csr_aliasing 3.000s 13.948us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 3.000s 56.149us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 3.000s 31.995us 1 1 100.00
rv_timer_csr_aliasing 3.000s 13.948us 1 1 100.00
V1 TOTAL 5 6 83.33
V2 random_reset rv_timer_random_reset 3.000s 36.043us 0 1 0.00
V2 disabled rv_timer_disabled 3.000s 472.854us 1 1 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 3.800m 107.921ms 1 1 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 3.800m 107.921ms 1 1 100.00
V2 stress rv_timer_stress_all 3.000s 113.302us 1 1 100.00
V2 alert_test rv_timer_alert_test 2.000s 15.217us 1 1 100.00
V2 intr_test rv_timer_intr_test 3.000s 19.118us 1 1 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 5.000s 585.969us 1 1 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 5.000s 585.969us 1 1 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 2.000s 14.434us 1 1 100.00
rv_timer_csr_rw 3.000s 31.995us 1 1 100.00
rv_timer_csr_aliasing 3.000s 13.948us 1 1 100.00
rv_timer_same_csr_outstanding 3.000s 28.742us 1 1 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 2.000s 14.434us 1 1 100.00
rv_timer_csr_rw 3.000s 31.995us 1 1 100.00
rv_timer_csr_aliasing 3.000s 13.948us 1 1 100.00
rv_timer_same_csr_outstanding 3.000s 28.742us 1 1 100.00
V2 TOTAL 7 8 87.50
V2S tl_intg_err rv_timer_sec_cm 3.000s 139.063us 1 1 100.00
rv_timer_tl_intg_err 4.000s 112.774us 1 1 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 4.000s 112.774us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 min_value rv_timer_min 3.000s 1.393us 0 1 0.00
V3 max_value rv_timer_max 2.000s 2.770us 0 1 0.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 3.000s 13.397us 0 1 0.00
V3 TOTAL 0 3 0.00
TOTAL 14 19 73.68

Failure Buckets