SPI_HOST Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.267m	1.998ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	18.609us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	18.497us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	59.179us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	25.012us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	32.840us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	18.497us	1	1	100.00
		spi_host_csr_aliasing	3.000s	25.012us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	33.851us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	16.052us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	71.076us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	170.090us	1	1	100.00
		spi_host_error_cmd	2.000s	21.572us	1	1	100.00
		spi_host_event	19.000s	2.685ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	75.187us	1	1	100.00
V2	speed	spi_host_speed	4.000s	75.187us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	75.187us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	7.000s	245.297us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	149.899us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	75.187us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	75.187us	1	1	100.00
V2	duplex	spi_host_smoke	1.267m	1.998ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.267m	1.998ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	441.440us	1	1	100.00
V2	spien	spi_host_spien	15.000s	2.481ms	1	1	100.00
V2	stall	spi_host_status_stall	28.000s	2.814ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	144.467us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	170.090us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	16.339us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	28.337us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	478.972us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	478.972us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	18.609us	1	1	100.00
		spi_host_csr_rw	2.000s	18.497us	1	1	100.00
		spi_host_csr_aliasing	3.000s	25.012us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	25.365us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	18.609us	1	1	100.00
		spi_host_csr_rw	2.000s	18.497us	1	1	100.00
		spi_host_csr_aliasing	3.000s	25.012us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	25.365us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	183.705us	1	1	100.00
		spi_host_sec_cm	3.000s	171.895us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	183.705us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.717m	10.828ms	1	1	100.00
		TOTAL			26	26	100.00