SYSRST_CTRL Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	13.000s	2.110ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	18.000s	2.467ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	16.000s	2.414ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.000s	2.525ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	27.000s	6.013ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.000s	2.067ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.000m	42.008ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	17.000s	2.520ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	13.000s	2.081ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.000s	2.067ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	17.000s	2.520ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	9.067m	155.365ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.100m	51.069ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	12.000s	3.349ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	5.000s	2.516ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	9.000s	2.516ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	7.000s	2.234ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	4.000s	3.195ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	9.000s	2.616ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	9.000s	4.343ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.417m	36.429ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	17.000s	9.170ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	12.000s	2.011ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.000s	2.025ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	13.000s	2.250ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	13.000s	2.250ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	27.000s	6.013ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.000s	2.067ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	17.000s	2.520ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	26.000s	5.387ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	27.000s	6.013ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.000s	2.067ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	17.000s	2.520ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	26.000s	5.387ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.883m	22.012ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	35.000s	43.127ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	35.000s	43.127ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	20.000s	3.663ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.90676096322872113745168615834580691529225961342490725431280503345481148102200
      Line 390, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-xcelium/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 2143805441 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
        UVM_INFO @ 2431305441 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
        UVM_INFO @ 4321305441 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
        UVM_INFO @ 4343027958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---