UART Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: c127aed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	5.000s	470.555us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	3.000s	12.392us	1	1	100.00
V1	csr_rw	uart_csr_rw	3.000s	36.732us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	4.000s	118.097us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	3.000s	28.295us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	3.000s	22.154us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	3.000s	36.732us	1	1	100.00
		uart_csr_aliasing	3.000s	28.295us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	34.000s	11.558ms	1	1	100.00
V2	parity	uart_smoke	5.000s	470.555us	1	1	100.00
		uart_tx_rx	34.000s	11.558ms	1	1	100.00
V2	parity_error	uart_intr	58.000s	40.859ms	1	1	100.00
		uart_rx_parity_err	1.333m	110.329ms	1	1	100.00
V2	watermark	uart_tx_rx	34.000s	11.558ms	1	1	100.00
		uart_intr	58.000s	40.859ms	1	1	100.00
V2	fifo_full	uart_fifo_full	24.000s	30.442ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.133m	343.286ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	17.000s	82.985ms	1	1	100.00
V2	rx_frame_err	uart_intr	58.000s	40.859ms	1	1	100.00
V2	rx_break_err	uart_intr	58.000s	40.859ms	1	1	100.00
V2	rx_timeout	uart_intr	58.000s	40.859ms	1	1	100.00
V2	perf	uart_perf	2.483m	28.232ms	1	1	100.00
V2	sys_loopback	uart_loopback	12.000s	8.314ms	1	1	100.00
V2	line_loopback	uart_loopback	12.000s	8.314ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	31.000s	32.410ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.917m	49.263ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	26.000s	6.265ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.000s	1.897ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	20.300m	194.622ms	1	1	100.00
V2	stress_all	uart_stress_all	13.650m	115.235ms	1	1	100.00
V2	alert_test	uart_alert_test	3.000s	29.389us	1	1	100.00
V2	intr_test	uart_intr_test	3.000s	14.129us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.000s	49.558us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.000s	49.558us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	3.000s	12.392us	1	1	100.00
		uart_csr_rw	3.000s	36.732us	1	1	100.00
		uart_csr_aliasing	3.000s	28.295us	1	1	100.00
		uart_same_csr_outstanding	3.000s	66.636us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	3.000s	12.392us	1	1	100.00
		uart_csr_rw	3.000s	36.732us	1	1	100.00
		uart_csr_aliasing	3.000s	28.295us	1	1	100.00
		uart_same_csr_outstanding	3.000s	66.636us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	3.000s	68.664us	1	1	100.00
		uart_tl_intg_err	3.000s	49.858us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.000s	49.858us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	34.000s	4.011ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.20243517292535433105100170408443058417404594453927741889715204521444815311270
      Line 82, in log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 28984752300 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 28984792300 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 28984832300 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 205 [0xcd]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 28984872300 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 28984912300 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata