CHIP Simulation Results

Monday September 15 2025 00:04:07 UTC

GitHub Revision: `c127aed`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	15.567m	2.834ms	1	1	100.00
		chip_sw_example_rom	5.817m	2.085ms	1	1	100.00
		chip_sw_example_manufacturer	12.933m	2.821ms	1	1	100.00
		chip_sw_example_concurrency	16.000m	2.910ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.967m	3.891ms	1	1	100.00
V1	csr_rw	chip_csr_rw	14.900m	4.143ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash			0	1	0.00
V1	csr_aliasing	chip_csr_aliasing			0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.867m	2.497ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	1	0.00
		chip_csr_rw	14.900m	4.143ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	30.000s	220.580us	0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	35.200m	4.108ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	35.200m	4.108ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	35.200m	4.108ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	35.683m	4.119ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	35.683m	4.119ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	42.700m	4.022ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	40.683m	4.144ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	40.800m	4.087ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate			0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq			0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed			0	1	0.00
V1		TOTAL			11	18	61.11
V2	chip_pin_mux	chip_padctrl_attributes	17.683m	4.440ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	17.683m	4.440ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	16.733m	3.010ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	26.767m	5.639ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	22.450m	4.038ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	12.617m	2.486ms	1	1	100.00
		chip_tap_straps_testunlock0	34.517m	4.085ms	1	1	100.00
		chip_tap_straps_rma	16.533m	2.733ms	1	1	100.00
		chip_tap_straps_prod	11.000m	2.497ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	18.200m	3.276ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses			0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	52.850m	5.095ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	52.850m	5.095ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	34.883m	4.005ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3.685h	18.435ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	19.733m	3.078ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter			0	1	0.00
		chip_sw_hmac_enc_jitter_en	20.133m	3.247ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	23.350m	3.266ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	41.150m	5.328ms	1	1	100.00
		chip_sw_clkmgr_jitter	15.250m	2.506ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	21.117m	3.604ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert			0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	35.000m	5.576ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	17.467m	3.288ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	35.000m	5.576ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	18.017m	3.500ms	1	1	100.00
		chip_sw_aes_smoketest	17.550m	3.359ms	1	1	100.00
		chip_sw_aon_timer_smoketest	21.533m	2.603ms	1	1	100.00
		chip_sw_clkmgr_smoketest	15.950m	2.257ms	1	1	100.00
		chip_sw_csrng_smoketest	12.083m	2.210ms	1	1	100.00
		chip_sw_entropy_src_smoketest			0	1	0.00
		chip_sw_gpio_smoketest	17.533m	3.448ms	1	1	100.00
		chip_sw_hmac_smoketest	22.183m	3.741ms	1	1	100.00
		chip_sw_kmac_smoketest	18.867m	3.186ms	1	1	100.00
		chip_sw_otbn_smoketest			0	1	0.00
		chip_sw_pwrmgr_smoketest	29.183m	6.409ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	31.633m	6.824ms	1	1	100.00
		chip_sw_rv_plic_smoketest	12.517m	2.396ms	1	1	100.00
		chip_sw_rv_timer_smoketest	16.667m	2.937ms	1	1	100.00
		chip_sw_rstmgr_smoketest	14.083m	2.125ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	12.583m	2.253ms	1	1	100.00
		chip_sw_uart_smoketest	15.717m	2.484ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	16.183m	2.333ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	32.450m	4.725ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	7.749h	60.760ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	2.781h	14.885ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	21.067m	5.498ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	21.850m	3.413ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	25.267m	3.249ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap			0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed			0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.833m	2.355ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.833m	2.355ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset	6.967m	3.891ms	1	1	100.00
		chip_csr_rw	14.900m	4.143ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset	6.967m	3.891ms	1	1	100.00
		chip_csr_rw	14.900m	4.143ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	1.783m	1.618ms	0	1	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	26.000s	44.277us	0	1	0.00
		xbar_smoke_large_delays	2.017m	8.245ms	0	1	0.00
		xbar_smoke_slow_rsp	2.017m	6.409ms	0	1	0.00
		xbar_random_zero_delays	1.067m	317.477us	0	1	0.00
		xbar_random_large_delays	8.900m	52.184ms	0	1	0.00
		xbar_random_slow_rsp	1.033m	2.977ms	0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	47.000s	414.453us	0	1	0.00
		xbar_error_and_unmapped_addr	1.300m	1.076ms	0	1	0.00
V2	xbar_error_cases	xbar_error_random	1.167m	968.975us	0	1	0.00
		xbar_error_and_unmapped_addr	1.300m	1.076ms	0	1	0.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.183m	958.530us	0	1	0.00
		xbar_access_same_device_slow_rsp	15.550m	51.651ms	0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.450m	1.440ms	0	1	0.00
V2	xbar_stress_all	xbar_stress_all	9.717m	9.124ms	0	1	0.00
		xbar_stress_all_with_error	1.367m	491.615us	0	1	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.533m	479.260us	0	1	0.00
		xbar_stress_all_with_reset_error	13.000m	12.140ms	0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	2.781h	14.885ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	49.250m	7.096ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	2.737h	14.326ms	0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2.203h	11.973ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2.861h	16.089ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2.903h	15.829ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	2.841h	16.061ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	2.725h	14.664ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	30.000s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	29.000s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	29.000s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	29.000s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	29.000s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	29.000s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	30.000s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.000s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.000s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.000s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.000s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.000s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	28.000s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	27.000s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	27.000s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	28.000s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	28.000s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	28.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	27.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	28.000s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	30.000s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	27.000s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	27.000s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	31.000s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	2.063h	11.892ms	1	1	100.00
		rom_e2e_asm_init_dev	2.873h	18.821ms	1	1	100.00
		rom_e2e_asm_init_prod	2.743h	15.599ms	1	1	100.00
		rom_e2e_asm_init_prod_end	2.851h	15.428ms	1	1	100.00
		rom_e2e_asm_init_rma	2.676h	14.411ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	2.698h	15.756ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	2.713h	15.007ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	2.704h	14.779ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	2.734h	16.033ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	18.983m	3.099ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	19.733m	3.078ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	12.283m	2.471ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	12.633m	2.140ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes			0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	19.250m	2.793ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	39.783m	4.859ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	45.367m	5.389ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0			0	1	0.00
		chip_plic_all_irqs_10	32.517m	3.021ms	1	1	100.00
		chip_plic_all_irqs_20	44.367m	4.062ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	20.517m	2.937ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info			0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	52.150m	5.194ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	16.117m	2.384ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	1.394h	10.870ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	1.244h	5.688ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	1.873h	8.074ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok			0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep			0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	28.800m	3.711ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	29.183m	6.409ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	28.800m	3.711ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	25.300m	7.500ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	50.450m	4.993ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness			0	1	0.00
		chip_sw_aes_idle	12.633m	2.140ms	1	1	100.00
		chip_sw_hmac_enc_idle	18.567m	2.961ms	1	1	100.00
		chip_sw_kmac_idle	16.867m	2.790ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	32.400m	3.817ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	40.933m	5.059ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	40.683m	5.722ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	30.317m	4.735ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri			0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	43.483m	3.521ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	47.333m	4.109ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	45.633m	4.444ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	48.717m	5.554ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	43.967m	4.192ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	42.783m	5.228ms	1	1	100.00
		chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc			0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	45.633m	4.444ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	48.717m	5.554ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	34.883m	4.005ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3.685h	18.435ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	19.733m	3.078ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter			0	1	0.00
		chip_sw_hmac_enc_jitter_en	20.133m	3.247ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	23.350m	3.266ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	41.150m	5.328ms	1	1	100.00
		chip_sw_clkmgr_jitter	15.250m	2.506ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	13.417m	2.668ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	41.017m	5.233ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3.155h	24.566ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	18.250m	2.716ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	16.483m	2.599ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	17.383m	3.028ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	38.367m	4.866ms	1	1	100.00
		chip_sw_flash_init_reduced_freq			0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq			0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	43.183m	4.234ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	30.517m	3.871ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	45.367m	5.389ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	1.244h	5.688ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	1.233h	4.979ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	31.967m	4.081ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	50.250m	6.728ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	14.817m	3.096ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency			0	1	0.00
		chip_sw_entropy_src_ast_rng_req	12.450m	3.005ms	1	1	100.00
		chip_sw_edn_entropy_reqs			0	1	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	12.450m	3.005ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	1.233h	4.979ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	17.317m	3.284ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init			0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access			0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	40.617m	4.378ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	34.883m	4.005ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked			0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init			0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	19.633m	2.761ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation			0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	33.983m	4.364ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked			0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	33.983m	4.364ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	33.983m	4.364ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	33.983m	4.364ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	33.983m	4.364ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	45.367m	5.389ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	38.750m	14.814ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	55.217m	4.571ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	53.167m	6.224ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	53.167m	6.224ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	19.617m	3.206ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	20.133m	3.247ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	18.567m	2.961ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	21.767m	2.993ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	32.217m	3.606ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	42.533m	4.661ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	49.900m	4.882ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2			0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	31.350m	4.344ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac			0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes			0	1	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	2.317h	11.116ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	16.900m	2.748ms	1	1	100.00
		chip_sw_kmac_mode_kmac	22.500m	3.306ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	23.350m	3.266ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation			0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	11.683m	2.423ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy			0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	16.867m	2.790ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	39.783m	4.859ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	12.617m	2.486ms	1	1	100.00
		chip_tap_straps_rma	16.533m	2.733ms	1	1	100.00
		chip_tap_straps_prod	11.000m	2.497ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	13.317m	2.260ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod			0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	33.983m	4.364ms	1	1	100.00
		chip_sw_flash_rma_unlocked			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	20.567m	2.940ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	50.300m	6.395ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma			0	1	0.00
		chip_sw_lc_ctrl_transition			0	1	0.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_rom_ctrl_integrity_check	46.183m	9.042ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	48.167m	6.994ms	1	1	100.00
		chip_prim_tl_access	38.750m	14.814ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	43.483m	3.521ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	47.333m	4.109ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	45.633m	4.444ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	48.717m	5.554ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	43.967m	4.192ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	42.783m	5.228ms	1	1	100.00
		chip_tap_straps_dev	12.617m	2.486ms	1	1	100.00
		chip_tap_straps_rma	16.533m	2.733ms	1	1	100.00
		chip_tap_straps_prod	11.000m	2.497ms	1	1	100.00
		chip_rv_dm_lc_disabled	24.050m	13.732ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	17.217m	3.767ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	9.083m	2.473ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	9.850m	3.575ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	17.817m	3.410ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks			0	1	0.00
		chip_rv_dm_lc_disabled	24.050m	13.732ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev			0	1	0.00
		chip_sw_lc_walkthrough_prod			0	1	0.00
		chip_sw_lc_walkthrough_prodend			0	1	0.00
		chip_sw_lc_walkthrough_rma			0	1	0.00
		chip_sw_lc_walkthrough_testunlocks			0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	6.833m	1.753ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	7.083m	2.110ms	1	1	100.00
		rom_volatile_raw_unlock	9.417m	2.919ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	3.626h	17.515ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3.685h	18.435ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	35.083m	4.027ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init			0	1	0.00
		chip_sw_otbn_mem_scramble	35.083m	4.027ms	1	1	100.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	43.550m	4.079ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	18.600m	3.180ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init			0	1	0.00
		chip_sw_otbn_mem_scramble	35.083m	4.027ms	1	1	100.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	43.550m	4.079ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	18.600m	3.180ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	41.717m	4.895ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	13.317m	2.260ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	20.567m	2.940ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	50.300m	6.395ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma			0	1	0.00
		chip_sw_lc_ctrl_transition			0	1	0.00
		chip_prim_tl_access	38.750m	14.814ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	38.750m	14.814ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock			0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	45.617m	8.187ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	28.283m	7.021ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	44.483m	6.250ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1.851h	13.014ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	1.720h	10.569ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	38.950m	3.968ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	45.617m	8.187ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.100m	2.682ms	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.100m	3.034ms	0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.483m	3.212ms	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs			0	1	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req			0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	20.600m	3.321ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	45.367m	5.389ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	46.183m	9.042ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	46.183m	9.042ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs			0	1	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	1	0.00
		chip_sw_pwrmgr_wdog_reset	38.950m	3.968ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	29.183m	6.409ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	24.600m	4.362ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	30.583m	4.934ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	32.950m	4.769ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info			0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	14.283m	2.728ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	45.367m	5.389ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	1.873h	8.074ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	58.983m	5.353ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	55.883m	4.228ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	24.483m	3.591ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	18.600m	3.180ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	30.583m	4.934ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	30.583m	4.934ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw			0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access			0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	24.600m	4.362ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	38.583m	4.358ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	38.133m	5.635ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	16.533m	2.733ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	24.050m	13.732ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0			0	1	0.00
		chip_plic_all_irqs_10	32.517m	3.021ms	1	1	100.00
		chip_plic_all_irqs_20	44.367m	4.062ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	20.200m	2.661ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	17.983m	2.821ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	2.781h	14.885ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	49.367m	5.107ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	16.917m	3.090ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	22.433m	3.082ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	19.967m	2.814ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	43.550m	4.079ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	41.150m	5.328ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble			0	1	0.00
		chip_sw_sleep_sram_ret_contents_scramble	55.967m	7.534ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	48.167m	6.994ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	45.367m	5.389ms	1	1	100.00
		chip_sw_data_integrity_escalation	52.850m	5.095ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	1	0.00
		chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	13.967m	3.333ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	28.400m	3.774ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	42.017m	4.597ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2.154h	11.621ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2.154h	11.621ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	34.833m	6.437ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	12.950m	3.012ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	14.200m	2.999ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	26.217m	3.063ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	33.400m	4.404ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg			0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi			0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	11.717m	2.642ms	1	1	100.00
V2		TOTAL			159	275	57.82
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	22.133m	3.057ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	9.600m	2.315ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	43.050m	3.315ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.627h	11.623ms	1	1	100.00
		rom_e2e_jtag_debug_dev	1.684h	11.915ms	1	1	100.00
		rom_e2e_jtag_debug_rma	1.621h	11.934ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	26.850m	4.649ms	1	1	100.00
		rom_e2e_jtag_inject_dev	23.567m	6.055ms	1	1	100.00
		rom_e2e_jtag_inject_rma	19.850m	4.255ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.829s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency			0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	35.650m	2.657ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	45.333m	3.523ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode			0	1	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	25.817m	2.574ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	53.067m	5.220ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	10.583m	2.605ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	40.133m	4.380ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	27.183m	5.306ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	30.983m	3.914ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs			0	1	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.627h	11.623ms	1	1	100.00
		rom_e2e_jtag_debug_dev	1.684h	11.915ms	1	1	100.00
		rom_e2e_jtag_debug_rma	1.621h	11.934ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	49.867m	4.564ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	45.367m	5.389ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	1	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	1	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	13.883m	3.022ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	35.683m	4.119ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream			0	1	0.00
V3		TOTAL			16	23	69.57
	Unmapped tests	chip_sival_flash_info_access	20.467m	3.566ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	42.467m	5.631ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	12.050m	2.832ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	22.300m	3.333ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	32.083m	4.013ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	19.598s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	17.333m	3.223ms	1	1	100.00
		TOTAL			193	325	59.38

Failure Buckets

Job timed out after * minutes has 70 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.112700157411297265090925831983009420396564463633191849235866081768766920978128
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_bit_bash/latest/run.log
```
  Job timed out after 180 minutes
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.45306487523781807253917968163228957530197240596551329055172495118028841848199
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_aliasing/latest/run.log
```
  Job timed out after 180 minutes
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.84448782918547556352085680070757515827511329201094294175452530871174449585665
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_same_csr_outstanding/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_sleep_pwm_pulses has 1 failures.
  - 0.chip_sw_sleep_pwm_pulses.13529061114298690839339233549527426357316556936874229527385252697487220568928
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_sleep_pwm_pulses/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_usbdev_dpi has 1 failures.
  - 0.chip_sw_usbdev_dpi.71593522041674944627626946468538657333963977262781438414702240256142285742127
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_usbdev_dpi/latest/run.log
```
  Job timed out after 120 minutes
```
- ... and 65 more tests.

xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_*/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_*/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database. has 18 failures:

Test xbar_smoke has 1 failures.

0.xbar_smoke.83141286800993761776457691312484373242193017089787983269560371554387640920324
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

Test xbar_smoke_zero_delays has 1 failures.

0.xbar_smoke_zero_delays.18991677345146250863571286810114669000027477148763931472925428798332524195921
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_zero_delays/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

Test xbar_smoke_large_delays has 1 failures.

0.xbar_smoke_large_delays.106744996368264567738002541534258847321527867291661927930878532116278887923314
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_large_delays/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

Test xbar_smoke_slow_rsp has 1 failures.

0.xbar_smoke_slow_rsp.74614875915988843386566393068140569119964915198296456621136403115666317187780
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

Test xbar_random has 1 failures.

0.xbar_random.94831731640575474021789409808115405035739069636925542175692380834430851605278
Line 297, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_random/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.

... and 13 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.107115676295289043158225575625526908370001533211114286320173856878211047797588
    Line 613, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.75321962174584076166180928542003699025440210195605679792915665844043567596260
    Line 648, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.87868761998615385695347536528085089823268000772929401279891765364107078772115
    Line 565, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.82162023356019121109267933244805860915447455126896011784563479037640255354490
    Line 615, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.115191409058601084132422289467914252192813778615101600530053736004727625567849
    Line 649, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.108995611388572341478156347600509307383321047693270613663371917872302621625973
    Line 547, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.79438272380205570160943254589582993972961664921262653059058453133064781649970
    Line 750, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.14785284931372939601225417316830543148489793820787767157317999755533830194103
    Line 555, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.71409065894721448518029726587381519689026120004062632540317605369551060144252
    Line 720, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.92947697812461911272292470983457577653881750732467622159890274658241068112367
    Line 536, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.93402836547708192937713700049831628076159834786697990550487635495553858004334
    Line 809, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.53868857853297746634762655634803464137042786914493744750497421919135948896540
    Line 557, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.97440862715808689659201652805009225110132433867173750021680023811447520635402
    Line 884, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_*/rtl/pwrmgr_slow_fsm.sv,362): (time * NS) Assertion IntRstReq_A has failed has 2 failures:

Test chip_sw_pwrmgr_main_power_glitch_reset has 1 failures.

0.chip_sw_pwrmgr_main_power_glitch_reset.14331631312096852283357037399243108829333518213142012388657458778732834721890
Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 2682336 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 2682.336000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 2682.336000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_pwrmgr_sleep_power_glitch_reset has 1 failures.

0.chip_sw_pwrmgr_sleep_power_glitch_reset.98064579172713436823375877030563667368700809056307824987858040208699892934329
Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 3211886 NS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 3211.886000 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 3211.886000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.87556819892125945498454497632414454067262494571192685072390705023914488012722
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.960s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.115038974671788900513587907537973019099199496035635539833681374801285388177973
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 3.762s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.105597332914186099426408589324441375937321357195949459560727064621194247905314
    Line 937, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.10119203878326693634126102567045310403712915489252591907672290406682026911145
    Line 882, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.14971161519834095477068039490887758873063823054333809590810653695737736268899
    Line 600, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.65878972173294314889784934592562483890216629145823478385438433705949884049517
    Line 805, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.64529383745338723513522782755354524737329035995335059768614908167554377511168
    Line 535, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3090.256116 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3090.256116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175370) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.15678318580024763262797237554831110694241035094541466170313520302360975174839
Line 415, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4933.731400 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175370) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4933.731400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_*/rtl/pwrmgr_slow_fsm.sv,362): Assertion IntRstReq_A has failed has 1 failures:
- Test chip_sw_pwrmgr_deep_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3548245673445914126395800575711933848557057999603628468540696218286948767555
    Line 412, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_earlgrey_ip_pwrmgr_0.1/rtl/pwrmgr_slow_fsm.sv,362): (time 3034192500 PS) Assertion tb.dut.top_earlgrey.u_pwrmgr_aon.u_slow_fsm.IntRstReq_A has failed
  UVM_ERROR @ 3034.192500 us: (pwrmgr_slow_fsm.sv:362) [ASSERT FAILED] IntRstReq_A
  UVM_INFO @ 3034.192500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.27223799319246206936011486749795737848017599349520303817122213849923261748301
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11620.921375 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11620.921375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.90462100544658359458000020840343057455344305169402135384391407696866766123741
    Line 459, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2792.977904 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2792.977904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.57393088285050189826325410415126695343037975930183019800747187373710143030035
    Line 469, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2383.672008 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2383.672008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.72978554583560707727241506285381711869590979456747738497563986387040204204576
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2993.002255 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2993.002255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@177468) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.109347036007029156232220232933268771195652097952038771580656536762409129415728
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2355.151304 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@177468) { a_addr: 'h107dc  a_data: 'h91672fbb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h1bd60  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2355.151304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:715) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.10638663849337885584404512390231891338390172278058452269137235655921430951142
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2315.012665 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2315.012665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:92) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.43056164385849100500413247359571793881184842908717074804256834326135958361638
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3413.294500 us: (chip_sw_power_idle_load_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3413.294500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:115) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.14741144225004688670912660100494983028866951464652104840922185675939569344574
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3249.076000 us: (chip_sw_power_sleep_load_vseq.sv:115) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3249.076000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.102181052260060380327931698600368057100580295627964973889701776360570275727182
    Line 451, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3314.607059 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3314.607059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 1 failures:
- Test rom_e2e_shutdown_exception_c has 1 failures.
  - 0.rom_e2e_shutdown_exception_c.62498336630881314905268778603289335619223570560894702944698937818424713392361
    Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 14326.098225 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  BF" == "OpenTitan:4001-0002-01x0d
  "
  UVM_INFO @ 14326.098225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 0.rom_e2e_shutdown_output.72547034858220243205367060552770297543951281131387670913532951080468622316351
    Line 450, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 7095.929898 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  BF" == "OpenTitan:4001-0002-01x0d
  "
  UVM_INFO @ 7095.929898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.74687017502206091445171505642011230562713700645071128808703345714285413425340
    Line 897, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.94726187253769929065466305763723433077247422724436949151680034154045024640582
    Line 847, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@178169) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.17797534964256356261785560308454049977477855317571173529368537123649680654472
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2496.503532 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@178169) { a_addr: 'h1050c  a_data: 'hbe8d44f5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h18ad4  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2496.503532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---