ADC_CTRL Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 42.000s 7 50 14.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 38.000s 0 5 0.00
V1 csr_rw adc_ctrl_csr_rw 42.000s 1 20 5.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 29.000s 0 5 0.00
V1 csr_aliasing adc_ctrl_csr_aliasing 29.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 38.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 42.000s 1 20 5.00
adc_ctrl_csr_aliasing 29.000s 0 5 0.00
V1 TOTAL 9 105 8.57
V2 filters_polled adc_ctrl_filters_polled 4.883m 331.547ms 3 50 6.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 4.600m 163.718ms 2 50 4.00
V2 filters_interrupt adc_ctrl_filters_interrupt 51.000s 0 50 0.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 46.000s 0 50 0.00
V2 filters_wakeup adc_ctrl_filters_wakeup 5.383m 189.330ms 3 50 6.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 2.217m 621.402ms 1 50 2.00
V2 filters_both adc_ctrl_filters_both 4.833m 165.510ms 1 50 2.00
V2 clock_gating adc_ctrl_clock_gating 2.850m 203.446ms 3 50 6.00
V2 poweron_counter adc_ctrl_poweron_counter 42.000s 1 50 2.00
V2 lowpower_counter adc_ctrl_lowpower_counter 52.000s 30.618ms 4 50 8.00
V2 fsm_reset adc_ctrl_fsm_reset 51.000s 0 50 0.00
V2 stress_all adc_ctrl_stress_all 11.767m 427.609ms 4 50 8.00
V2 alert_test adc_ctrl_alert_test 46.000s 4 50 8.00
V2 intr_test adc_ctrl_intr_test 46.000s 3 50 6.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 38.000s 1 20 5.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 38.000s 1 20 5.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 38.000s 0 5 0.00
adc_ctrl_csr_rw 42.000s 1 20 5.00
adc_ctrl_csr_aliasing 29.000s 0 5 0.00
adc_ctrl_same_csr_outstanding 38.000s 0 20 0.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 38.000s 0 5 0.00
adc_ctrl_csr_rw 42.000s 1 20 5.00
adc_ctrl_csr_aliasing 29.000s 0 5 0.00
adc_ctrl_same_csr_outstanding 38.000s 0 20 0.00
V2 TOTAL 30 740 4.05
V2S tl_intg_err adc_ctrl_sec_cm 30.000s 0 5 0.00
adc_ctrl_tl_intg_err 38.000s 0 20 0.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 38.000s 0 20 0.00
V2S TOTAL 0 25 0.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 47.000s 1 50 2.00
V3 TOTAL 1 50 2.00
TOTAL 40 920 4.35

Failure Buckets