996a7b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 7.000s | 98.267us | 1 | 1 | 100.00 |
| V1 | smoke | aes_smoke | 39.000s | 4 | 50 | 8.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 39.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 39.000s | 1 | 20 | 5.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 6 | 106 | 5.66 | |||
| V2 | algorithm | aes_smoke | 39.000s | 4 | 50 | 8.00 | |
| aes_config_error | 51.000s | 2 | 50 | 4.00 | |||
| aes_stress | 47.000s | 0 | 50 | 0.00 | |||
| V2 | key_length | aes_smoke | 39.000s | 4 | 50 | 8.00 | |
| aes_config_error | 51.000s | 2 | 50 | 4.00 | |||
| aes_stress | 47.000s | 0 | 50 | 0.00 | |||
| V2 | back2back | aes_stress | 47.000s | 0 | 50 | 0.00 | |
| aes_b2b | 46.000s | 5 | 50 | 10.00 | |||
| V2 | backpressure | aes_stress | 47.000s | 0 | 50 | 0.00 | |
| V2 | multi_message | aes_smoke | 39.000s | 4 | 50 | 8.00 | |
| aes_config_error | 51.000s | 2 | 50 | 4.00 | |||
| aes_stress | 47.000s | 0 | 50 | 0.00 | |||
| aes_alert_reset | 42.000s | 4 | 50 | 8.00 | |||
| V2 | failure_test | aes_man_cfg_err | 51.000s | 3 | 50 | 6.00 | |
| aes_config_error | 51.000s | 2 | 50 | 4.00 | |||
| aes_alert_reset | 42.000s | 4 | 50 | 8.00 | |||
| V2 | trigger_clear_test | aes_clear | 55.000s | 3 | 50 | 6.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 26.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 42.000s | 4 | 50 | 8.00 | |
| V2 | stress | aes_stress | 47.000s | 0 | 50 | 0.00 | |
| V2 | sideload | aes_stress | 47.000s | 0 | 50 | 0.00 | |
| aes_sideload | 42.000s | 2 | 50 | 4.00 | |||
| V2 | deinitialization | aes_deinit | 43.000s | 3 | 50 | 6.00 | |
| V2 | stress_all | aes_stress_all | 1.117m | 8.065ms | 3 | 10 | 30.00 |
| V2 | alert_test | aes_alert_test | 43.000s | 4 | 50 | 8.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 43.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 43.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 47.000s | 1 | 20 | 5.00 | |||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 54.000s | 0 | 20 | 0.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 47.000s | 1 | 20 | 5.00 | |||
| V2 | TOTAL | 30 | 501 | 5.99 | |||
| V2S | reseeding | aes_reseed | 38.000s | 6 | 50 | 12.00 | |
| V2S | fault_inject | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 38.000s | 0 | 20 | 0.00 | |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 38.000s | 0 | 20 | 0.00 | |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 38.000s | 0 | 20 | 0.00 | |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 38.000s | 0 | 20 | 0.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 46.000s | 0 | 20 | 0.00 | |
| V2S | tl_intg_err | aes_sec_cm | 42.000s | 0 | 5 | 0.00 | |
| aes_tl_intg_err | 38.000s | 3 | 20 | 15.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 38.000s | 3 | 20 | 15.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 42.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 38.000s | 0 | 20 | 0.00 | |
| V2S | sec_cm_main_config_sparse | aes_smoke | 39.000s | 4 | 50 | 8.00 | |
| aes_stress | 47.000s | 0 | 50 | 0.00 | |||
| aes_alert_reset | 42.000s | 4 | 50 | 8.00 | |||
| aes_core_fi | 46.000s | 7 | 70 | 10.00 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 38.000s | 0 | 20 | 0.00 | |
| V2S | sec_cm_aux_config_regwen | aes_readability | 46.000s | 1 | 50 | 2.00 | |
| aes_stress | 47.000s | 0 | 50 | 0.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 47.000s | 0 | 50 | 0.00 | |
| aes_sideload | 42.000s | 2 | 50 | 4.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 46.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 46.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 46.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 46.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 46.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 47.000s | 0 | 50 | 0.00 | |
| V2S | sec_cm_key_masking | aes_stress | 47.000s | 0 | 50 | 0.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |||
| aes_ctr_fi | 47.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_ctr_fi | 47.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |||
| aes_ctr_fi | 47.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 42.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |||
| aes_ctr_fi | 47.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |||
| aes_ctr_fi | 47.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_ctr_fi | 47.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 43.000s | 1 | 50 | 2.00 | |
| aes_control_fi | 51.000s | 15 | 300 | 5.00 | |||
| aes_cipher_fi | 54.000s | 20 | 350 | 5.71 | |||
| V2S | TOTAL | 56 | 985 | 5.69 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 50.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 92 | 1602 | 5.74 |
Job returned non-zero exit code has 1507 failures:
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.104188996302209777894871077648231910220103890414698554833464181213737081241302
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:28:58 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 47 failures.
0.aes_deinit.40481074860174022753759937639363605635943826501759779372108058781701531785495
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:28:53 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_deinit.89900040987739393100245082999289108190151462760320364793710850394127920019397
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:28:59 UTC (total: 00:00:14)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
Test aes_man_cfg_err has 47 failures.
0.aes_man_cfg_err.112539785074489284169976615221939792371327345075779461065658066069148044755143
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:29:10 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_man_cfg_err.50782437891790944979257387940722930423157510569851265572548644835733043031555
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:29:14 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
Test aes_readability has 49 failures.
0.aes_readability.23663623207128360885842870364185585962361696951141927204582753247762547829083
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:29:03 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_readability.33823975680428112263841316621118256528237461691046346906333671188892086541775
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:29:03 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
Test aes_smoke has 46 failures.
0.aes_smoke.7060154671156891134876668385257886170942102727577971615374525311360043099895
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:29:11 UTC (total: 00:00:37)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_smoke.43697958582876736630004743484464584273449638469311990163721312663687612549329
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:29:04 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 44 more failures.
... and 26 more tests.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
2.aes_stress_all_with_rand_reset.77771931002996432506576611217992449446140963826106340054311339754688802840485
Line 150, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 223491048 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 223491048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:
65.aes_cipher_fi.37130028307050078411021791190560186918961323761175491990079470209269426619648
Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/65.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10022347224 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10022347224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
315.aes_cipher_fi.55335029896510734165446509886922997936637561473114451628881411739146075100257
Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/315.aes_cipher_fi/latest/run.log
Job timed out after 1 minutes