996a7b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 21.000s | 0 | 1 | 0.00 | |
| V1 | smoke | aes_smoke | 47.000s | 4 | 50 | 8.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 54.000s | 3 | 20 | 15.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 42.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 42.000s | 2 | 5 | 40.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 55.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 54.000s | 3 | 20 | 15.00 | |
| aes_csr_aliasing | 42.000s | 2 | 5 | 40.00 | |||
| V1 | TOTAL | 9 | 106 | 8.49 | |||
| V2 | algorithm | aes_smoke | 47.000s | 4 | 50 | 8.00 | |
| aes_config_error | 42.000s | 5 | 50 | 10.00 | |||
| aes_stress | 43.000s | 1 | 50 | 2.00 | |||
| V2 | key_length | aes_smoke | 47.000s | 4 | 50 | 8.00 | |
| aes_config_error | 42.000s | 5 | 50 | 10.00 | |||
| aes_stress | 43.000s | 1 | 50 | 2.00 | |||
| V2 | back2back | aes_stress | 43.000s | 1 | 50 | 2.00 | |
| aes_b2b | 46.000s | 4 | 50 | 8.00 | |||
| V2 | backpressure | aes_stress | 43.000s | 1 | 50 | 2.00 | |
| V2 | multi_message | aes_smoke | 47.000s | 4 | 50 | 8.00 | |
| aes_config_error | 42.000s | 5 | 50 | 10.00 | |||
| aes_stress | 43.000s | 1 | 50 | 2.00 | |||
| aes_alert_reset | 1.167m | 5 | 50 | 10.00 | |||
| V2 | failure_test | aes_man_cfg_err | 44.000s | 1 | 50 | 2.00 | |
| aes_config_error | 42.000s | 5 | 50 | 10.00 | |||
| aes_alert_reset | 1.167m | 5 | 50 | 10.00 | |||
| V2 | trigger_clear_test | aes_clear | 50.000s | 3 | 50 | 6.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 25.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 1.167m | 5 | 50 | 10.00 | |
| V2 | stress | aes_stress | 43.000s | 1 | 50 | 2.00 | |
| V2 | sideload | aes_stress | 43.000s | 1 | 50 | 2.00 | |
| aes_sideload | 46.000s | 3 | 50 | 6.00 | |||
| V2 | deinitialization | aes_deinit | 44.000s | 1 | 50 | 2.00 | |
| V2 | stress_all | aes_stress_all | 35.000s | 1 | 10 | 10.00 | |
| V2 | alert_test | aes_alert_test | 51.000s | 3 | 50 | 6.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 46.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 46.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 54.000s | 3 | 20 | 15.00 | |||
| aes_csr_aliasing | 42.000s | 2 | 5 | 40.00 | |||
| aes_same_csr_outstanding | 39.000s | 1 | 20 | 5.00 | |||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 54.000s | 3 | 20 | 15.00 | |||
| aes_csr_aliasing | 42.000s | 2 | 5 | 40.00 | |||
| aes_same_csr_outstanding | 39.000s | 1 | 20 | 5.00 | |||
| V2 | TOTAL | 29 | 501 | 5.79 | |||
| V2S | reseeding | aes_reseed | 46.000s | 7 | 50 | 14.00 | |
| V2S | fault_inject | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 38.000s | 1 | 20 | 5.00 | |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 38.000s | 1 | 20 | 5.00 | |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 38.000s | 1 | 20 | 5.00 | |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 38.000s | 1 | 20 | 5.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 39.000s | 0 | 20 | 0.00 | |
| V2S | tl_intg_err | aes_sec_cm | 21.000s | 1 | 5 | 20.00 | |
| aes_tl_intg_err | 43.000s | 2 | 20 | 10.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 43.000s | 2 | 20 | 10.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 1.167m | 5 | 50 | 10.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 38.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_main_config_sparse | aes_smoke | 47.000s | 4 | 50 | 8.00 | |
| aes_stress | 43.000s | 1 | 50 | 2.00 | |||
| aes_alert_reset | 1.167m | 5 | 50 | 10.00 | |||
| aes_core_fi | 50.000s | 4 | 70 | 5.71 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 38.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_aux_config_regwen | aes_readability | 48.000s | 3 | 50 | 6.00 | |
| aes_stress | 43.000s | 1 | 50 | 2.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 43.000s | 1 | 50 | 2.00 | |
| aes_sideload | 46.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 48.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 48.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 48.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 48.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 48.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_key_masking | aes_stress | 43.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |||
| aes_ctr_fi | 48.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_ctr_fi | 48.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |||
| aes_ctr_fi | 48.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 1.167m | 5 | 50 | 10.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |||
| aes_ctr_fi | 48.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |||
| aes_ctr_fi | 48.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_ctr_fi | 48.000s | 3 | 50 | 6.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 43.000s | 2 | 50 | 4.00 | |
| aes_control_fi | 55.000s | 11 | 300 | 3.67 | |||
| aes_cipher_fi | 47.000s | 17 | 350 | 4.86 | |||
| V2S | TOTAL | 51 | 985 | 5.18 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 34.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 89 | 1602 | 5.56 |
Job returned non-zero exit code has 1507 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.39247132020070867922987344421380247520733293245848780717960199730624469529145
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_wake_up/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:06:42 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.61477157458984474832724700119767365811233921050652459048372516617101380063160
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:06:47 UTC (total: 00:00:25)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 49 failures.
0.aes_deinit.10297500111933013308998892158141904224032415040742853629960421427052833250788
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:06:43 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_deinit.29903190241425493603236970782193355598174378264330459239385563279793224181954
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:06:56 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
Test aes_man_cfg_err has 49 failures.
0.aes_man_cfg_err.109821159503138072203821130263367309553873335315105822574102167212209717098585
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:07:00 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_man_cfg_err.107569068052049608328797327592723546072550728902863655206778147455870737948236
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:07:09 UTC (total: 00:00:33)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
Test aes_readability has 47 failures.
0.aes_readability.18299699838374574211724807252686027293885360264206104565621446498021608315544
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:07:00 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_readability.92190495351688859238179638227568587696395879405425264384623698026046313791376
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 05:06:56 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
... and 27 more tests.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
0.aes_control_fi.3805458546152267419164855680204393213631782605350259301895933254898590944796
Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
UVM_FATAL @ 10008974040 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008974040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
76.aes_control_fi.6264936449460918333237476161060133326614273189012287923315858093223666605712
Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/76.aes_control_fi/latest/run.log
UVM_FATAL @ 10005268552 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005268552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 2 failures:
74.aes_control_fi.41514923090373202468818528094813850738030546551891998594717125550552454211696
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/74.aes_control_fi/latest/run.log
Job timed out after 1 minutes
117.aes_control_fi.43485444955282121131953436823282094529335658157029146013101317274714147703100
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/117.aes_control_fi/latest/run.log
Job timed out after 1 minutes
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
5.aes_stress_all_with_rand_reset.63851293651200165036742543351763343933320179529143276509723532870874024962182
Line 610, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1296636076 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1296636076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:
135.aes_cipher_fi.114388745260943118377272149833275018835772349812393404420159214384788149054562
Line 134, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/135.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10004318502 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10004318502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---