996a7b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 42.000s | 2 | 50 | 4.00 | |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 30.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | csrng_csr_rw | 42.000s | 0 | 20 | 0.00 | |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 29.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | csrng_csr_aliasing | 29.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 46.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 42.000s | 0 | 20 | 0.00 | |
| csrng_csr_aliasing | 29.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 2 | 105 | 1.90 | |||
| V2 | interrupts | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| V2 | alerts | csrng_alert | 55.000s | 24 | 500 | 4.80 | |
| V2 | err | csrng_err | 55.000s | 26 | 500 | 5.20 | |
| V2 | cmds | csrng_cmds | 3.567m | 22.087ms | 3 | 50 | 6.00 |
| V2 | life cycle | csrng_cmds | 3.567m | 22.087ms | 3 | 50 | 6.00 |
| V2 | stress_all | csrng_stress_all | 7.517m | 42.406ms | 1 | 50 | 2.00 |
| V2 | intr_test | csrng_intr_test | 46.000s | 4 | 50 | 8.00 | |
| V2 | alert_test | csrng_alert_test | 42.000s | 3 | 50 | 6.00 | |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 38.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_illegal_access | csrng_tl_errors | 38.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 30.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 42.000s | 0 | 20 | 0.00 | |||
| csrng_csr_aliasing | 29.000s | 0 | 5 | 0.00 | |||
| csrng_same_csr_outstanding | 38.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 30.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 42.000s | 0 | 20 | 0.00 | |||
| csrng_csr_aliasing | 29.000s | 0 | 5 | 0.00 | |||
| csrng_same_csr_outstanding | 38.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 77 | 1440 | 5.35 | |||
| V2S | tl_intg_err | csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |
| csrng_tl_intg_err | 38.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_config_regwen | csrng_regwen | 46.000s | 2 | 50 | 4.00 | |
| csrng_csr_rw | 42.000s | 0 | 20 | 0.00 | |||
| V2S | sec_cm_config_mubi | csrng_alert | 55.000s | 24 | 500 | 4.80 | |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 7.517m | 42.406ms | 1 | 50 | 2.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 55.000s | 24 | 500 | 4.80 | |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 7.517m | 42.406ms | 1 | 50 | 2.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 55.000s | 24 | 500 | 4.80 | |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 38.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| csrng_sec_cm | 42.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 47.000s | 15 | 200 | 7.50 | |
| csrng_err | 55.000s | 26 | 500 | 5.20 | |||
| V2S | TOTAL | 4 | 75 | 5.33 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 38.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 83 | 1630 | 5.09 |
Job returned non-zero exit code has 1544 failures:
0.csrng_smoke.39655606321761115949139457306285217988569947311587698157659691496934762132672
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:17 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_smoke.79622202814576683414996743001279438303627382465883147243084906453608024546597
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:25 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
0.csrng_cmds.6129357015706119364408620645092479572559833702565221159354446739076149908565
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:26 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_cmds.2344161002784186647547093178900422628056868390549564884176849898030342149218
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_cmds/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:20 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.csrng_stress_all.43852351407930363062313762070601276933763099406723317551180769547376332115190
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:18 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_stress_all.6523099450381344149495085660440105073913161206794192641134313295112156075411
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:21 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
0.csrng_intr.72683985704283696302542251039479492149992723112270237453459383071582563277796
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:27 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_intr.39008795170617990373556280017305897435773441658459602333511591754473572992011
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:26 UTC (total: 00:00:25)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 182 more failures.
0.csrng_alert.64899991031581754953165503838446765745018715410047515568748080889720543106867
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:19 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_alert.86097671928303133629908448657397100332771692529158611803969645398716857068114
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 03:43:30 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 474 more failures.
UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 2 failures:
207.csrng_err.47319509651823992272711280027851981084100980971851766284040294961141178905969
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/207.csrng_err/latest/run.log
UVM_FATAL @ 13543176 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 13543176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
454.csrng_err.27424769797756830338315810291310554323271645124557553720123818736091318866291
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/454.csrng_err/latest/run.log
UVM_FATAL @ 9534020 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 9534020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 1 failures:
57.csrng_intr.46461501561530582597583053206800750190986868104031800926433541626344562312161
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/57.csrng_intr/latest/run.log
UVM_FATAL @ 106999697 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
----| PATH NOT FOUND
UVM_INFO @ 106999697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---