EDN Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 51.000s 1 50 2.00
V1 csr_hw_reset edn_csr_hw_reset 46.000s 0 5 0.00
V1 csr_rw edn_csr_rw 38.000s 0 20 0.00
V1 csr_bit_bash edn_csr_bit_bash 38.000s 0 5 0.00
V1 csr_aliasing edn_csr_aliasing 30.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 42.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 38.000s 0 20 0.00
edn_csr_aliasing 30.000s 0 5 0.00
V1 TOTAL 2 105 1.90
V2 firmware edn_genbits 59.000s 8 300 2.67
V2 csrng_commands edn_genbits 59.000s 8 300 2.67
V2 genbits edn_genbits 59.000s 8 300 2.67
V2 interrupts edn_intr 46.000s 1 50 2.00
V2 alerts edn_alert 55.000s 9 200 4.50
V2 errs edn_err 46.000s 0 100 0.00
V2 disable edn_disable 47.000s 2 50 4.00
edn_disable_auto_req_mode 50.000s 2 50 4.00
V2 stress_all edn_stress_all 47.000s 2 50 4.00
V2 intr_test edn_intr_test 55.000s 0 50 0.00
V2 alert_test edn_alert_test 42.000s 2 50 4.00
V2 tl_d_oob_addr_access edn_tl_errors 47.000s 2 20 10.00
V2 tl_d_illegal_access edn_tl_errors 47.000s 2 20 10.00
V2 tl_d_outstanding_access edn_csr_hw_reset 46.000s 0 5 0.00
edn_csr_rw 38.000s 0 20 0.00
edn_csr_aliasing 30.000s 0 5 0.00
edn_same_csr_outstanding 47.000s 0 20 0.00
V2 tl_d_partial_access edn_csr_hw_reset 46.000s 0 5 0.00
edn_csr_rw 38.000s 0 20 0.00
edn_csr_aliasing 30.000s 0 5 0.00
edn_same_csr_outstanding 47.000s 0 20 0.00
V2 TOTAL 28 940 2.98
V2S tl_intg_err edn_sec_cm 38.000s 0 5 0.00
edn_tl_intg_err 47.000s 0 20 0.00
V2S sec_cm_config_regwen edn_regwen 38.000s 0 10 0.00
V2S sec_cm_config_mubi edn_alert 55.000s 9 200 4.50
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 38.000s 0 5 0.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ctr_redun edn_sec_cm 38.000s 0 5 0.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 55.000s 9 200 4.50
edn_sec_cm 38.000s 0 5 0.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 55.000s 9 200 4.50
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 47.000s 0 20 0.00
V2S TOTAL 0 35 0.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 50.000s 1 50 2.00
V3 TOTAL 1 50 2.00
TOTAL 31 1130 2.74

Failure Buckets