ENTROPY_SRC/RNG_4BITS Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 50.000s 2 50 4.00
V1 csr_hw_reset entropy_src_csr_hw_reset 37.000s 1 5 20.00
V1 csr_rw entropy_src_csr_rw 1.000m 0 20 0.00
V1 csr_bit_bash entropy_src_csr_bit_bash 46.000s 0 5 0.00
V1 csr_aliasing entropy_src_csr_aliasing 46.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 38.000s 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 1.000m 0 20 0.00
entropy_src_csr_aliasing 46.000s 0 5 0.00
V1 TOTAL 3 105 2.86
V2 firmware entropy_src_smoke 50.000s 2 50 4.00
entropy_src_rng 4.350m 20.023ms 17 300 5.67
entropy_src_fw_ov 4.883m 19.034ms 23 300 7.67
V2 firmware_mode entropy_src_fw_ov 4.883m 19.034ms 23 300 7.67
V2 rng_mode entropy_src_rng 4.350m 20.023ms 17 300 5.67
V2 rng_max_rate entropy_src_rng_max_rate 7.633m 17.040ms 15 400 3.75
V2 health_checks entropy_src_rng 4.350m 20.023ms 17 300 5.67
V2 conditioning entropy_src_rng 4.350m 20.023ms 17 300 5.67
V2 interrupts entropy_src_rng 4.350m 20.023ms 17 300 5.67
entropy_src_intr 52.000s 1 50 2.00
V2 alerts entropy_src_rng 4.350m 20.023ms 17 300 5.67
entropy_src_functional_alerts 51.000s 3 50 6.00
V2 stress_all entropy_src_stress_all 47.000s 8.547ms 2 50 4.00
V2 functional_errors entropy_src_functional_errors 55.000s 54 1000 5.40
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 43.000s 2 50 4.00
V2 intr_test entropy_src_intr_test 38.000s 4 50 8.00
V2 alert_test entropy_src_alert_test 47.000s 0 50 0.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 38.000s 1 20 5.00
V2 tl_d_illegal_access entropy_src_tl_errors 38.000s 1 20 5.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 37.000s 1 5 20.00
entropy_src_csr_rw 1.000m 0 20 0.00
entropy_src_csr_aliasing 46.000s 0 5 0.00
entropy_src_same_csr_outstanding 50.000s 1 20 5.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 37.000s 1 5 20.00
entropy_src_csr_rw 1.000m 0 20 0.00
entropy_src_csr_aliasing 46.000s 0 5 0.00
entropy_src_same_csr_outstanding 50.000s 1 20 5.00
V2 TOTAL 123 2340 5.26
V2S tl_intg_err entropy_src_sec_cm 38.000s 0 5 0.00
entropy_src_tl_intg_err 38.000s 1 20 5.00
V2S sec_cm_config_regwen entropy_src_rng 4.350m 20.023ms 17 300 5.67
entropy_src_cfg_regwen 46.000s 2 50 4.00
V2S sec_cm_config_mubi entropy_src_rng 4.350m 20.023ms 17 300 5.67
V2S sec_cm_config_redun entropy_src_rng 4.350m 20.023ms 17 300 5.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.350m 20.023ms 17 300 5.67
entropy_src_fw_ov 4.883m 19.034ms 23 300 7.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 55.000s 54 1000 5.40
entropy_src_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 55.000s 54 1000 5.40
entropy_src_sec_cm 38.000s 0 5 0.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.350m 20.023ms 17 300 5.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 55.000s 54 1000 5.40
entropy_src_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 55.000s 54 1000 5.40
entropy_src_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 55.000s 54 1000 5.40
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 51.000s 3 50 6.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 38.000s 1 20 5.00
V2S TOTAL 3 75 4.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.300m 19.024ms 5 50 10.00
V3 TOTAL 5 50 10.00
TOTAL 134 2570 5.21

Failure Buckets