HMAC Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 34.000s 0 10 0.00
V1 csr_hw_reset hmac_csr_hw_reset 45.000s 0 5 0.00
V1 csr_rw hmac_csr_rw 46.000s 1 20 5.00
V1 csr_bit_bash hmac_csr_bit_bash 34.000s 0 5 0.00
V1 csr_aliasing hmac_csr_aliasing 38.000s 1 5 20.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 38.000s 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 46.000s 1 20 5.00
hmac_csr_aliasing 38.000s 1 5 20.00
V1 TOTAL 2 65 3.08
V2 long_msg hmac_long_msg 29.000s 1 10 10.00
V2 back_pressure hmac_back_pressure 41.000s 5.002ms 2 25 8.00
V2 test_vectors hmac_test_sha256_vectors 3.050m 9.230ms 1 30 3.33
hmac_test_sha384_vectors 4.933m 23.379ms 5 75 6.67
hmac_test_sha512_vectors 47.000s 1 75 1.33
hmac_test_hmac256_vectors 46.000s 4 50 8.00
hmac_test_hmac384_vectors 42.000s 3 60 5.00
hmac_test_hmac512_vectors 47.000s 4 75 5.33
V2 burst_wr hmac_burst_wr 42.000s 7 50 14.00
V2 datapath_stress hmac_datapath_stress 1.433m 4.320ms 1 10 10.00
V2 error hmac_error 56.000s 44.660ms 1 10 10.00
V2 wipe_secret hmac_wipe_secret 38.000s 0 10 0.00
V2 save_and_restore hmac_smoke 34.000s 0 10 0.00
hmac_long_msg 29.000s 1 10 10.00
hmac_back_pressure 41.000s 5.002ms 2 25 8.00
hmac_datapath_stress 1.433m 4.320ms 1 10 10.00
hmac_burst_wr 42.000s 7 50 14.00
hmac_stress_all 6.117m 67.929ms 2 50 4.00
V2 fifo_empty_status_interrupt hmac_smoke 34.000s 0 10 0.00
hmac_long_msg 29.000s 1 10 10.00
hmac_back_pressure 41.000s 5.002ms 2 25 8.00
hmac_datapath_stress 1.433m 4.320ms 1 10 10.00
hmac_wipe_secret 38.000s 0 10 0.00
hmac_test_sha256_vectors 3.050m 9.230ms 1 30 3.33
hmac_test_sha384_vectors 4.933m 23.379ms 5 75 6.67
hmac_test_sha512_vectors 47.000s 1 75 1.33
hmac_test_hmac256_vectors 46.000s 4 50 8.00
hmac_test_hmac384_vectors 42.000s 3 60 5.00
hmac_test_hmac512_vectors 47.000s 4 75 5.33
V2 wide_digest_configurable_key_length hmac_smoke 34.000s 0 10 0.00
hmac_long_msg 29.000s 1 10 10.00
hmac_back_pressure 41.000s 5.002ms 2 25 8.00
hmac_datapath_stress 1.433m 4.320ms 1 10 10.00
hmac_burst_wr 42.000s 7 50 14.00
hmac_error 56.000s 44.660ms 1 10 10.00
hmac_wipe_secret 38.000s 0 10 0.00
hmac_test_sha256_vectors 3.050m 9.230ms 1 30 3.33
hmac_test_sha384_vectors 4.933m 23.379ms 5 75 6.67
hmac_test_sha512_vectors 47.000s 1 75 1.33
hmac_test_hmac256_vectors 46.000s 4 50 8.00
hmac_test_hmac384_vectors 42.000s 3 60 5.00
hmac_test_hmac512_vectors 47.000s 4 75 5.33
hmac_stress_all 6.117m 67.929ms 2 50 4.00
V2 stress_all hmac_stress_all 6.117m 67.929ms 2 50 4.00
V2 alert_test hmac_alert_test 42.000s 2 50 4.00
V2 intr_test hmac_intr_test 46.000s 4 50 8.00
V2 tl_d_oob_addr_access hmac_tl_errors 54.000s 1 20 5.00
V2 tl_d_illegal_access hmac_tl_errors 54.000s 1 20 5.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 45.000s 0 5 0.00
hmac_csr_rw 46.000s 1 20 5.00
hmac_csr_aliasing 38.000s 1 5 20.00
hmac_same_csr_outstanding 55.000s 2 20 10.00
V2 tl_d_partial_access hmac_csr_hw_reset 45.000s 0 5 0.00
hmac_csr_rw 46.000s 1 20 5.00
hmac_csr_aliasing 38.000s 1 5 20.00
hmac_same_csr_outstanding 55.000s 2 20 10.00
V2 TOTAL 41 670 6.12
V2S tl_intg_err hmac_sec_cm 30.000s 0 5 0.00
hmac_tl_intg_err 46.000s 0 20 0.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 46.000s 0 20 0.00
V2S TOTAL 0 25 0.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 34.000s 0 10 0.00
V3 stress_reset hmac_stress_reset 38.000s 1 25 4.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.283m 6.035ms 3 35 8.57
V3 TOTAL 4 60 6.67
Unmapped tests hmac_directed 21.000s 0 1 0.00
TOTAL 47 821 5.72

Failure Buckets