I2C Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 1.467m 2.854ms 5 50 10.00
V1 target_smoke i2c_target_smoke 43.000s 2 50 4.00
V1 csr_hw_reset i2c_csr_hw_reset 30.000s 0 5 0.00
V1 csr_rw i2c_csr_rw 42.000s 0 20 0.00
V1 csr_bit_bash i2c_csr_bit_bash 38.000s 0 5 0.00
V1 csr_aliasing i2c_csr_aliasing 42.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 42.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 42.000s 0 20 0.00
i2c_csr_aliasing 42.000s 0 5 0.00
V1 TOTAL 8 155 5.16
V2 host_error_intr i2c_host_error_intr 43.000s 0 50 0.00
V2 host_stress_all i2c_host_stress_all 42.000m 9.827ms 0 50 0.00
V2 host_maxperf i2c_host_perf 4.817m 11.963ms 2 50 4.00
V2 host_override i2c_host_override 46.000s 5 50 10.00
V2 host_fifo_watermark i2c_host_fifo_watermark 50.000s 0 50 0.00
V2 host_fifo_overflow i2c_host_fifo_overflow 47.000s 0 50 0.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 43.000s 6 50 12.00
i2c_host_fifo_fmt_empty 46.000s 1 50 2.00
i2c_host_fifo_reset_rx 46.000s 6 50 12.00
V2 host_fifo_full i2c_host_fifo_full 9.617m 3.700ms 6 50 12.00
V2 host_timeout i2c_host_stretch_timeout 55.000s 3 50 6.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 42.000s 1 50 2.00
V2 target_glitch i2c_target_glitch 30.000s 0 2 0.00
V2 target_stress_all i2c_target_stress_all 42.000s 1 50 2.00
V2 target_maxperf i2c_target_perf 55.000s 5 50 10.00
V2 target_fifo_empty i2c_target_stress_rd 50.000s 2 50 4.00
i2c_target_intr_smoke 42.000s 4 50 8.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 46.000s 2 50 4.00
i2c_target_fifo_reset_tx 50.000s 1 50 2.00
V2 target_fifo_full i2c_target_stress_wr 48.467m 44.966ms 1 50 2.00
i2c_target_stress_rd 50.000s 2 50 4.00
i2c_target_intr_stress_wr 42.000s 0 50 0.00
V2 target_timeout i2c_target_timeout 46.000s 0 50 0.00
V2 target_clock_stretch i2c_target_stretch 5.333m 2.654ms 3 50 6.00
V2 bad_address i2c_target_bad_addr 49.000s 2 50 4.00
V2 target_mode_glitch i2c_target_hrst 43.000s 0 50 0.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 50.000s 5 50 10.00
i2c_target_fifo_watermarks_tx 42.000s 1 50 2.00
V2 host_mode_config_perf i2c_host_perf 4.817m 11.963ms 2 50 4.00
i2c_host_perf_precise 43.000s 2 50 4.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 55.000s 3 50 6.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 50.000s 3 50 6.00
V2 target_mode_nack_generation i2c_target_nack_acqfull 47.000s 0 50 0.00
i2c_target_nack_acqfull_addr 55.000s 2 50 4.00
i2c_target_nack_txstretch 46.000s 6 50 12.00
V2 host_mode_halt_on_nak i2c_host_may_nack 47.000s 2 50 4.00
V2 target_mode_smbus_maxlen i2c_target_smbus_maxlen 47.000s 1 50 2.00
V2 alert_test i2c_alert_test 42.000s 4 50 8.00
V2 intr_test i2c_intr_test 46.000s 4 50 8.00
V2 tl_d_oob_addr_access i2c_tl_errors 42.000s 2 20 10.00
V2 tl_d_illegal_access i2c_tl_errors 42.000s 2 20 10.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 30.000s 0 5 0.00
i2c_csr_rw 42.000s 0 20 0.00
i2c_csr_aliasing 42.000s 0 5 0.00
i2c_same_csr_outstanding 38.000s 3 20 15.00
V2 tl_d_partial_access i2c_csr_hw_reset 30.000s 0 5 0.00
i2c_csr_rw 42.000s 0 20 0.00
i2c_csr_aliasing 42.000s 0 5 0.00
i2c_same_csr_outstanding 38.000s 3 20 15.00
V2 TOTAL 86 1792 4.80
V2S tl_intg_err i2c_tl_intg_err 46.000s 0 20 0.00
i2c_sec_cm 47.000s 0 5 0.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 46.000s 0 20 0.00
V2S TOTAL 0 25 0.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 42.000s 0 10 0.00
V3 target_error_intr i2c_target_unexp_stop 54.000s 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 46.000s 0 10 0.00
V3 TOTAL 0 70 0.00
TOTAL 94 2042 4.60

Failure Buckets