996a7b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 46.000s | 3 | 50 | 6.00 | |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | pattgen_csr_rw | 38.000s | 1 | 20 | 5.00 | |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 29.000s | 1 | 5 | 20.00 | |
| V1 | csr_aliasing | pattgen_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 34.000s | 3 | 20 | 15.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 38.000s | 1 | 20 | 5.00 | |
| pattgen_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 8 | 105 | 7.62 | |||
| V2 | perf | pattgen_perf | 17.383m | 600.000ms | 1 | 50 | 2.00 |
| V2 | cnt_rollover | cnt_rollover | 47.000s | 1 | 50 | 2.00 | |
| V2 | error | pattgen_error | 46.000s | 3 | 50 | 6.00 | |
| V2 | stress_all | pattgen_stress_all | 1.724h | 2.690s | 1 | 50 | 2.00 |
| V2 | alert_test | pattgen_alert_test | 39.000s | 1 | 50 | 2.00 | |
| V2 | intr_test | pattgen_intr_test | 46.000s | 3 | 50 | 6.00 | |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| pattgen_csr_rw | 38.000s | 1 | 20 | 5.00 | |||
| pattgen_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| pattgen_same_csr_outstanding | 48.000s | 1 | 20 | 5.00 | |||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| pattgen_csr_rw | 38.000s | 1 | 20 | 5.00 | |||
| pattgen_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| pattgen_same_csr_outstanding | 48.000s | 1 | 20 | 5.00 | |||
| V2 | TOTAL | 11 | 340 | 3.24 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 50.000s | 1 | 20 | 5.00 | |
| pattgen_sec_cm | 38.000s | 0 | 5 | 0.00 | |||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 50.000s | 1 | 20 | 5.00 | |
| V2S | TOTAL | 1 | 25 | 4.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 1.183m | 20.552ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 38.000s | 1 | 50 | 2.00 | ||
| TOTAL | 21 | 570 | 3.68 |
Job returned non-zero exit code has 542 failures:
0.pattgen_smoke.50126510805452453631961741125089879321520563223698166979458914045092930505031
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:18 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_smoke.13507053259170933772944935171127217720499979784005742881491388642223768530787
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:22 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.pattgen_perf.39773877075383015916555289384586109678144039237375005366269042368448513109618
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:10 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_perf.109000517984968057030537872907521943816767945542686569056897811814014099677854
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:31 UTC (total: 00:00:37)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.pattgen_error.79383578834964653020019282796159041368733129145692187811295001760791770917268
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:36 UTC (total: 00:00:46)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_error.112771136946729007477226640314300921857072145229774156667501912252225237299043
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:23 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.cnt_rollover.9994137602073195974264854517859714388741313635897857616788180357091779174136
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.cnt_rollover/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:19 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.cnt_rollover.68830848714196017496843755915239814794737952777042194554367858626594148925378
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.cnt_rollover/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:15 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
0.pattgen_inactive_level.51082294370165316013005287935318038100975445949242543135097830989338519170375
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:11 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_inactive_level.21521480009941566362062254909999261267633954777877312805420715207331042532275
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 00:22:12 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
2.pattgen_stress_all_with_rand_reset.51317692568794451382200929799827066500923972618262663044214891208163482998113
Line 148, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2228716723 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2228721517 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2228721517 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2228803149 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
23.pattgen_stress_all_with_rand_reset.104800543425795065808414360253226111269390836053423119521211161261159253666173
Line 265, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6509027121 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 6509060212 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6509060212 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 6509185213 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 2 more failures.
Job timed out after * minutes has 2 failures:
Test pattgen_perf has 1 failures.
38.pattgen_perf.3572506709268667047117560906993624929515814669168233187851635123356788873130
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_perf/latest/run.log
Job timed out after 60 minutes
Test pattgen_stress_all has 1 failures.
41.pattgen_stress_all.98768530722315000902461513133650541121716517728846916769305131119225402243294
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
9.pattgen_perf.84709364751191041714332033509195931485436082926664891269831550952172619401385
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---