996a7b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 21.000s | 0 | 2 | 0.00 | |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 42.000s | 0 | 20 | 0.00 | |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 34.000s | 1 | 5 | 20.00 | |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 29.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 29.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 38.000s | 0 | 20 | 0.00 | |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 42.000s | 0 | 20 | 0.00 | |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 42.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 33.000s | 0 | 2 | 0.00 | |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 38.000s | 0 | 2 | 0.00 | |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 34.000s | 1 | 2 | 50.00 | |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 21.000s | 0 | 2 | 0.00 | |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 21.000s | 0 | 2 | 0.00 | |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 33.000s | 0 | 2 | 0.00 | |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 21.000s | 0 | 2 | 0.00 | |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 38.000s | 0 | 8 | 0.00 | |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 33.000s | 0 | 2 | 0.00 | |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 34.000s | 0 | 2 | 0.00 | |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 30.000s | 0 | 2 | 0.00 | |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 34.000s | 1 | 2 | 50.00 | |
| V1 | rom_read_access | rv_dm_rom_read_access | 29.000s | 0 | 2 | 0.00 | |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 34.000s | 1 | 5 | 20.00 | |
| V1 | csr_rw | rv_dm_csr_rw | 42.000s | 1 | 20 | 5.00 | |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 37.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 39.000s | 616.151us | 1 | 5 | 20.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 54.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 39.000s | 616.151us | 1 | 5 | 20.00 |
| rv_dm_csr_rw | 42.000s | 1 | 20 | 5.00 | |||
| V1 | mem_walk | rv_dm_mem_walk | 29.000s | 0 | 5 | 0.00 | |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 30.000s | 0 | 5 | 0.00 | |
| V1 | TOTAL | 5 | 180 | 2.78 | |||
| V2 | idcode | rv_dm_smoke | 21.000s | 0 | 2 | 0.00 | |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 34.000s | 0 | 2 | 0.00 | |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 42.000s | 1 | 2 | 50.00 | |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 33.000s | 297.468us | 1 | 2 | 50.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 21.000s | 0 | 2 | 0.00 | |
| V2 | sba | rv_dm_sba_tl_access | 8.933m | 300.000ms | 0 | 20 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 42.000s | 0 | 20 | 0.00 | |||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 7.683m | 300.000ms | 0 | 20 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 51.000s | 0 | 20 | 0.00 | |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 29.000s | 0 | 2 | 0.00 | |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 42.000s | 0 | 2 | 0.00 | |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 26.000s | 0 | 2 | 0.00 | |
| V2 | hart_unavail | rv_dm_hart_unavail | 34.000s | 1 | 5 | 20.00 | |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 29.000s | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm_rand_reset | 37.000s | 0 | 10 | 0.00 | |||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 21.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | rv_dm_stress_all | 50.000s | 5 | 50 | 10.00 | |
| V2 | alert_test | rv_dm_alert_test | 43.000s | 0 | 50 | 0.00 | |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 46.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 46.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 39.000s | 616.151us | 1 | 5 | 20.00 |
| rv_dm_csr_hw_reset | 34.000s | 1 | 5 | 20.00 | |||
| rv_dm_csr_rw | 42.000s | 1 | 20 | 5.00 | |||
| rv_dm_same_csr_outstanding | 42.000s | 2 | 20 | 10.00 | |||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 39.000s | 616.151us | 1 | 5 | 20.00 |
| rv_dm_csr_hw_reset | 34.000s | 1 | 5 | 20.00 | |||
| rv_dm_csr_rw | 42.000s | 1 | 20 | 5.00 | |||
| rv_dm_same_csr_outstanding | 42.000s | 2 | 20 | 10.00 | |||
| V2 | TOTAL | 10 | 251 | 3.98 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 38.000s | 0 | 5 | 0.00 | |
| rv_dm_tl_intg_err | 51.000s | 0 | 20 | 0.00 | |||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 51.000s | 0 | 20 | 0.00 | |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 42.000s | 0 | 2 | 0.00 | |
| rv_dm_debug_disabled | 38.000s | 0 | 2 | 0.00 | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 42.000s | 0 | 2 | 0.00 | |
| rv_dm_debug_disabled | 38.000s | 0 | 2 | 0.00 | |||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 21.000s | 0 | 2 | 0.00 | |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 42.000s | 0 | 10 | 0.00 | |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 30.000s | 1 | 4 | 25.00 | |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 30.000s | 1 | 4 | 25.00 | |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 42.000s | 0 | 10 | 0.00 | |
| V2S | TOTAL | 1 | 41 | 2.44 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 30.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 29.000s | 0 | 1 | 0.00 | ||
| TOTAL | 16 | 483 | 3.31 |
Job returned non-zero exit code has 463 failures:
Test rv_dm_csr_aliasing has 4 failures.
0.rv_dm_csr_aliasing.38075513269724289662027122383273964941580212410393868281906823925758922849227
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_aliasing/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:33:06 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_csr_aliasing.50451373993648950233377557191205134739533443564871972518304720328423333444151
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_aliasing/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:33:29 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 2 more failures.
Test rv_dm_smoke has 2 failures.
0.rv_dm_smoke.113762062106336867397786830336628418197269634902645884296807541473213531693123
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:35:37 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_smoke.55466713548172436886471964303221985153820242334877162861879932906740979771341
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:35:58 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test rv_dm_tap_fsm has 1 failures.
0.rv_dm_tap_fsm.49224518256944164480759912997324815444651690314976488091972639546622484147139
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:35:46 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.
0.rv_dm_jtag_dtm_csr_hw_reset.460783641063304037800944870861072646263728863576818512577499594087340851547
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:33:24 UTC (total: 00:00:37)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_jtag_dtm_csr_hw_reset.55144237433688238469830183579648304764211689375123506366302165857928268009067
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:33:21 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 3 more failures.
Test rv_dm_jtag_dtm_csr_rw has 20 failures.
0.rv_dm_jtag_dtm_csr_rw.112859885006592925254840149404252463788171972480213828610401219758293710467840
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_rw/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:33:21 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_jtag_dtm_csr_rw.19561309532414556914431264541682277382363965326385479747608827779165550332579
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_rw/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 01:33:40 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 18 more failures.
... and 48 more tests.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test rv_dm_bad_sba_tl_access has 1 failures.
9.rv_dm_bad_sba_tl_access.78668509652976334465918605008864575199001227583646636929218065334488751720398
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/9.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_sba_tl_access has 1 failures.
13.rv_dm_sba_tl_access.76810622302935753266221768386354107856415249927662862506857698551535122040039
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24205) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.rv_dm_tl_errors.77071581078651337837868280703018962014229398685261830960410250690697432920856
Line 86, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 141648734 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24205) { a_addr: 'h8a705754 a_data: 'h7f634f08 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h57 a_opcode: 'h4 a_user: 'h181ad d_param: 'h0 d_source: 'h57 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 141648734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24160) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
8.rv_dm_csr_mem_rw_with_rand_reset.58304927072414206824504248873897196634887338051730129535721142403768524793986
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/8.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 23238600 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@24160) { a_addr: 'h4faf34d0 a_data: 'h9abe74c1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc4 a_opcode: 'h4 a_user: 'h1ab8f d_param: 'h0 d_source: 'hc4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 23238600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---