RV_TIMER Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 38.000s 0 20 0.00
V1 csr_hw_reset rv_timer_csr_hw_reset 30.000s 1 5 20.00
V1 csr_rw rv_timer_csr_rw 42.000s 0 20 0.00
V1 csr_bit_bash rv_timer_csr_bit_bash 38.000s 0 5 0.00
V1 csr_aliasing rv_timer_csr_aliasing 34.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 38.000s 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 42.000s 0 20 0.00
rv_timer_csr_aliasing 34.000s 0 5 0.00
V1 TOTAL 1 75 1.33
V2 random_reset rv_timer_random_reset 42.000s 0 20 0.00
V2 disabled rv_timer_disabled 38.000s 1 20 5.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 42.000s 0 10 0.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 42.000s 0 10 0.00
V2 stress rv_timer_stress_all 42.000s 0 20 0.00
V2 alert_test rv_timer_alert_test 54.000s 1 50 2.00
V2 intr_test rv_timer_intr_test 59.000s 2 50 4.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 42.000s 0 20 0.00
V2 tl_d_illegal_access rv_timer_tl_errors 42.000s 0 20 0.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 30.000s 1 5 20.00
rv_timer_csr_rw 42.000s 0 20 0.00
rv_timer_csr_aliasing 34.000s 0 5 0.00
rv_timer_same_csr_outstanding 51.000s 2 20 10.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 30.000s 1 5 20.00
rv_timer_csr_rw 42.000s 0 20 0.00
rv_timer_csr_aliasing 34.000s 0 5 0.00
rv_timer_same_csr_outstanding 51.000s 2 20 10.00
V2 TOTAL 6 210 2.86
V2S tl_intg_err rv_timer_sec_cm 38.000s 0 5 0.00
rv_timer_tl_intg_err 43.000s 1 20 5.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 43.000s 1 20 5.00
V2S TOTAL 1 25 4.00
V3 min_value rv_timer_min 38.000s 0 10 0.00
V3 max_value rv_timer_max 38.000s 0 10 0.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 38.000s 0 20 0.00
V3 TOTAL 0 40 0.00
TOTAL 8 350 2.29

Failure Buckets