SPI_HOST Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 51.000s 1 50 2.00
V1 csr_hw_reset spi_host_csr_hw_reset 30.000s 0 5 0.00
V1 csr_rw spi_host_csr_rw 38.000s 0 20 0.00
V1 csr_bit_bash spi_host_csr_bit_bash 42.000s 1 5 20.00
V1 csr_aliasing spi_host_csr_aliasing 51.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 54.000s 2 20 10.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 38.000s 0 20 0.00
spi_host_csr_aliasing 51.000s 0 5 0.00
V1 mem_walk spi_host_mem_walk 46.000s 0 5 0.00
V1 mem_partial_access spi_host_mem_partial_access 1.950m 0 5 0.00
V1 TOTAL 4 115 3.48
V2 performance spi_host_performance 46.000s 5 50 10.00
V2 error_event_intr spi_host_overflow_underflow 49.000s 4 50 8.00
spi_host_error_cmd 1.000m 2 50 4.00
spi_host_event 59.000s 3 50 6.00
V2 clock_rate spi_host_speed 39.000s 4 50 8.00
V2 speed spi_host_speed 39.000s 4 50 8.00
V2 chip_select_timing spi_host_speed 39.000s 4 50 8.00
V2 sw_reset spi_host_sw_reset 56.000s 5 50 10.00
V2 passthrough_mode spi_host_passthrough_mode 47.000s 2 50 4.00
V2 cpol_cpha spi_host_speed 39.000s 4 50 8.00
V2 full_cycle spi_host_speed 39.000s 4 50 8.00
V2 duplex spi_host_smoke 51.000s 1 50 2.00
V2 tx_rx_only spi_host_smoke 51.000s 1 50 2.00
V2 stress_all spi_host_stress_all 52.000s 5 50 10.00
V2 spien spi_host_spien 2.383m 18.827ms 4 50 8.00
V2 stall spi_host_status_stall 1.167m 2 50 4.00
V2 Idlecsbactive spi_host_idlecsbactive 50.000s 3 50 6.00
V2 data_fifo_status spi_host_overflow_underflow 49.000s 4 50 8.00
V2 alert_test spi_host_alert_test 47.000s 3 50 6.00
V2 intr_test spi_host_intr_test 47.000s 1 50 2.00
V2 tl_d_oob_addr_access spi_host_tl_errors 46.000s 0 20 0.00
V2 tl_d_illegal_access spi_host_tl_errors 46.000s 0 20 0.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 30.000s 0 5 0.00
spi_host_csr_rw 38.000s 0 20 0.00
spi_host_csr_aliasing 51.000s 0 5 0.00
spi_host_same_csr_outstanding 42.000s 0 20 0.00
V2 tl_d_partial_access spi_host_csr_hw_reset 30.000s 0 5 0.00
spi_host_csr_rw 38.000s 0 20 0.00
spi_host_csr_aliasing 51.000s 0 5 0.00
spi_host_same_csr_outstanding 42.000s 0 20 0.00
V2 TOTAL 43 690 6.23
V2S tl_intg_err spi_host_tl_intg_err 54.000s 2 20 10.00
spi_host_sec_cm 34.000s 1 5 20.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 54.000s 2 20 10.00
V2S TOTAL 3 25 12.00
Unmapped tests spi_host_upper_range_clkdiv 45.000s 4.730ms 1 10 10.00
TOTAL 51 840 6.07

Failure Buckets