996a7b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 51.000s | 3 | 50 | 6.00 | |
| V1 | csr_hw_reset | uart_csr_hw_reset | 31.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | uart_csr_rw | 39.000s | 0 | 20 | 0.00 | |
| V1 | csr_bit_bash | uart_csr_bit_bash | 30.000s | 2 | 5 | 40.00 | |
| V1 | csr_aliasing | uart_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 38.000s | 1 | 20 | 5.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 39.000s | 0 | 20 | 0.00 | |
| uart_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 6 | 105 | 5.71 | |||
| V2 | base_random_seq | uart_tx_rx | 1.617m | 206.993ms | 4 | 50 | 8.00 |
| V2 | parity | uart_smoke | 51.000s | 3 | 50 | 6.00 | |
| uart_tx_rx | 1.617m | 206.993ms | 4 | 50 | 8.00 | ||
| V2 | parity_error | uart_intr | 59.000s | 0 | 50 | 0.00 | |
| uart_rx_parity_err | 47.000s | 1 | 50 | 2.00 | |||
| V2 | watermark | uart_tx_rx | 1.617m | 206.993ms | 4 | 50 | 8.00 |
| uart_intr | 59.000s | 0 | 50 | 0.00 | |||
| V2 | fifo_full | uart_fifo_full | 2.383m | 97.737ms | 3 | 50 | 6.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 47.000s | 1 | 50 | 2.00 | |
| V2 | fifo_reset | uart_fifo_reset | 2.833m | 95.190ms | 17 | 300 | 5.67 |
| V2 | rx_frame_err | uart_intr | 59.000s | 0 | 50 | 0.00 | |
| V2 | rx_break_err | uart_intr | 59.000s | 0 | 50 | 0.00 | |
| V2 | rx_timeout | uart_intr | 59.000s | 0 | 50 | 0.00 | |
| V2 | perf | uart_perf | 6.717m | 17.418ms | 3 | 50 | 6.00 |
| V2 | sys_loopback | uart_loopback | 43.000s | 2 | 50 | 4.00 | |
| V2 | line_loopback | uart_loopback | 43.000s | 2 | 50 | 4.00 | |
| V2 | rx_noise_filter | uart_noise_filter | 43.000s | 0 | 50 | 0.00 | |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 52.000s | 5 | 50 | 10.00 | |
| V2 | tx_overide | uart_tx_ovrd | 39.000s | 1 | 50 | 2.00 | |
| V2 | rx_oversample | uart_rx_oversample | 42.000s | 2 | 50 | 4.00 | |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 2.300m | 148.510ms | 2 | 50 | 4.00 |
| V2 | stress_all | uart_stress_all | 14.033m | 324.789ms | 2 | 50 | 4.00 |
| V2 | alert_test | uart_alert_test | 47.000s | 1 | 50 | 2.00 | |
| V2 | intr_test | uart_intr_test | 50.000s | 2 | 50 | 4.00 | |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 38.000s | 2 | 20 | 10.00 | |
| V2 | tl_d_illegal_access | uart_tl_errors | 38.000s | 2 | 20 | 10.00 | |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 31.000s | 0 | 5 | 0.00 | |
| uart_csr_rw | 39.000s | 0 | 20 | 0.00 | |||
| uart_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| uart_same_csr_outstanding | 56.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 31.000s | 0 | 5 | 0.00 | |
| uart_csr_rw | 39.000s | 0 | 20 | 0.00 | |||
| uart_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| uart_same_csr_outstanding | 56.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 48 | 1090 | 4.40 | |||
| V2S | tl_intg_err | uart_sec_cm | 34.000s | 0 | 5 | 0.00 | |
| uart_tl_intg_err | 38.000s | 2 | 20 | 10.00 | |||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 38.000s | 2 | 20 | 10.00 | |
| V2S | TOTAL | 2 | 25 | 8.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 48.000s | 3 | 100 | 3.00 | |
| V3 | TOTAL | 3 | 100 | 3.00 | |||
| TOTAL | 59 | 1320 | 4.47 |
Job returned non-zero exit code has 1255 failures:
0.uart_smoke.26513980697325724050300442187622337709996481771995958821064448456891496124285
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:10 UTC (total: 00:00:37)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_smoke.76605341471410184751726557962841727848619961088355418706622823068539485068949
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:09 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.uart_tx_rx.109119811789285917600707066322970242764510595802968714936927698428345309227147
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tx_rx/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:01:53 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_tx_rx.77246096008670436734715708321217277711553781552628551075512499841323679308778
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tx_rx/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:16 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 44 more failures.
0.uart_fifo_full.56428836559939996435079918302634668629463402957285408129945441239784951815549
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_full/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:02 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_fifo_full.29100048851407043641370331446869956553452506004862838900245876401137047139188
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_full/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:03 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.uart_fifo_overflow.24031800523557627254791837625411526517909138909054943977188281200250006970695
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_overflow/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:16 UTC (total: 00:00:42)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_fifo_overflow.107903887992308424965268691050067082998213883695223898263891856460971432851546
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_overflow/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:12 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
0.uart_fifo_reset.110232627335800032717742254753125916299735076125825098919496138765439940560644
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:01:55 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_fifo_reset.111294340719785556433609353461679956940219892606502611583901064092785643353951
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 16, 2025 at 04:02:03 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 281 more failures.
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 3 failures:
21.uart_noise_filter.17267119837908522545929201863488581936709573249138106558419592876197520655219
Line 82, in log /nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_noise_filter/latest/run.log
UVM_ERROR @ 6373832087 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 7364112087 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 7656072087 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 13, clk_pulses: 0
UVM_ERROR @ 7656112087 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 7656152087 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (187 [0xbb] vs 255 [0xff]) reg name: uart_reg_block.rdata
32.uart_noise_filter.23850730987290614309530215964204535078852125032177861637430036977355011506324
Line 84, in log /nightly/current_run/scratch/master/uart-sim-xcelium/32.uart_noise_filter/latest/run.log
UVM_ERROR @ 3937611422 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3941211422 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3948291422 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3951691422 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3955051422 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
... and 1 more failures.
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark has 1 failures:
30.uart_stress_all.5327364460346868594005493474778537182305547138921085583173999293556695833121
Line 112, in log /nightly/current_run/scratch/master/uart-sim-xcelium/30.uart_stress_all/latest/run.log
UVM_ERROR @ 323467032963 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 323467032963 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_ERROR @ 323507338763 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 323507338763 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_ERROR @ 323592052371 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
43.uart_noise_filter.16075377038562005914468735076082098714688703511660162012556844308198609763818
Line 84, in log /nightly/current_run/scratch/master/uart-sim-xcelium/43.uart_noise_filter/latest/run.log
UVM_ERROR @ 11478903510 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 11478939224 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 11478974938 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (223 [0xdf] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 11770079752 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 11775543994 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
66.uart_stress_all_with_rand_reset.105483852323870747655774442747901967564099362359227064337273109865122758911386
Line 196, in log /nightly/current_run/scratch/master/uart-sim-xcelium/66.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16381815782 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 16381815782 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 16381815782 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 16460108075 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 3
UVM_ERROR @ 16460149742 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty