USBDEV Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: 996a7b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 43.000s 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 42.000s 0 5 0.00
V1 csr_rw usbdev_csr_rw 38.000s 1 20 5.00
V1 csr_bit_bash usbdev_csr_bit_bash 42.000s 0 5 0.00
V1 csr_aliasing usbdev_csr_aliasing 37.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 46.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 38.000s 1 20 5.00
usbdev_csr_aliasing 37.000s 0 5 0.00
V1 mem_walk usbdev_mem_walk 42.000s 0 5 0.00
V1 mem_partial_access usbdev_mem_partial_access 38.000s 1 5 20.00
V1 TOTAL 3 115 2.61
V2 in_trans usbdev_in_trans 44.000s 3 50 6.00
V2 data_toggle_clear usbdev_data_toggle_clear 47.000s 1 50 2.00
V2 phy_pins_sense usbdev_phy_pins_sense 38.000s 3 50 6.00
V2 av_buffer usbdev_av_buffer 54.000s 4 50 8.00
V2 rx_fifo usbdev_pkt_buffer 55.000s 2 50 4.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 38.000s 0 1 0.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 30.000s 0 1 0.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 52.000s 0 50 0.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 37.000s 0 5 0.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 29.000s 0 1 0.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 42.000s 0 1 0.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 51.000s 2 50 4.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 47.000s 1 50 2.00
usbdev_stream_len_max 44.000s 1 50 2.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 56.000s 6 50 12.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 43.000s 2 50 4.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 50.000s 3 50 6.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 50.000s 3 50 6.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 46.000s 1 50 2.00
V2 out_stall usbdev_out_stall 46.000s 3 50 6.00
V2 in_stall usbdev_in_stall 44.000s 3 50 6.00
V2 out_iso usbdev_out_iso 44.000s 2 50 4.00
V2 in_iso usbdev_in_iso 51.000s 4 50 8.00
V2 pkt_received usbdev_pkt_received 51.000s 1 50 2.00
V2 pkt_sent usbdev_pkt_sent 47.000s 4 50 8.00
V2 disconnected usbdev_disconnected 42.000s 4 50 8.00
V2 host_lost usbdev_host_lost 29.000s 0 1 0.00
V2 link_reset usbdev_link_reset 26.000s 0 1 0.00
V2 link_suspend usbdev_link_suspend 42.000s 0 50 0.00
V2 link_resume usbdev_link_resume 49.000s 26.465ms 2 50 4.00
V2 av_empty usbdev_av_empty 42.000s 0 5 0.00
V2 rx_full usbdev_rx_full 1.383m 1 50 2.00
V2 av_overflow usbdev_av_overflow 51.000s 0 5 0.00
V2 link_in_err usbdev_link_in_err 51.000s 4 50 8.00
V2 rx_crc_err usbdev_rx_crc_err 42.000s 6 50 12.00
V2 rx_pid_err usbdev_rx_pid_err 37.000s 0 5 0.00
V2 rx_bitstuff_err usbdev_bitstuff_err 46.000s 4 50 8.00
V2 link_out_err usbdev_link_out_err 2.000s 386.068us 1 1 100.00
V2 enable usbdev_enable 43.000s 2 50 4.00
V2 resume_link_active usbdev_resume_link_active 50.000s 0 20 0.00
V2 device_address usbdev_device_address 1.467m 3 50 6.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 25.000s 0 1 0.00
V2 setup_stage usbdev_setup_stage 47.000s 3 50 6.00
V2 endpoint_access usbdev_endpoint_access 47.000s 1 50 2.00
V2 disable_endpoint usbdev_disable_endpoint 38.000s 0 50 0.00
V2 endpoint_types usbdev_endpoint_types 55.000s 11 200 5.50
V2 out_trans_nak usbdev_out_trans_nak 47.000s 2 50 4.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 47.000s 3 50 6.00
V2 nak_trans usbdev_nak_trans 55.000s 5 50 10.00
V2 stall_trans usbdev_stall_trans 46.000s 2 50 4.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 29.000s 1 5 20.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 43.000s 2 50 4.00
V2 pending_in_trans usbdev_pending_in_trans 47.000s 3 50 6.00
V2 streaming_test usbdev_streaming_out 52.000s 2.869ms 1 50 2.00
V2 max_clock_error_untracked usbdev_freq_hiclk 38.000s 0 5 0.00
usbdev_freq_loclk 38.000s 0 5 0.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 38.000s 0 5 0.00
usbdev_freq_loclk_max 3.750m 117.937ms 1 5 20.00
V2 max_phase_error usbdev_freq_phase 3.950m 117.154ms 1 5 20.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 56.000s 3.152ms 3 50 6.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 55.000s 3.030ms 3 50 6.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 50.000s 4 50 8.00
V2 device_timeout usbdev_device_timeout 48.000s 2 50 4.00
V2 packet_buffer usbdev_pkt_buffer 55.000s 2 50 4.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 26.000s 0 1 0.00
V2 aon_wake_resume usbdev_aon_wake_resume 57.000s 29.823ms 2 50 4.00
V2 aon_wake_reset usbdev_aon_wake_reset 50.000s 1 50 2.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 1.350m 1 50 2.00
V2 invalid_sync usbdev_invalid_sync 51.000s 2.862ms 3 50 6.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 46.000s 2 50 4.00
V2 low_speed_traffic usbdev_low_speed_traffic 1.100m 3.662ms 2 50 4.00
V2 rand_bus_resets usbdev_rand_bus_resets 38.000s 8.407ms 1 10 10.00
V2 rand_disconnects usbdev_rand_bus_disconnects 37.000s 0 10 0.00
V2 rand_suspends usbdev_rand_suspends 42.000s 0 10 0.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 43.000s 2 25 8.00
usbdev_max_usb_traffic 38.000s 0 15 0.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 34.000s 0 10 0.00
V2 in_packet_retraction usbdev_iso_retraction 1.383m 11.292ms 2 50 4.00
V2 data_toggle_restore usbdev_data_toggle_restore 43.000s 2 50 4.00
V2 setup_priority usbdev_setup_priority 29.000s 0 5 0.00
V2 fifo_resets usbdev_fifo_rst 54.000s 4 50 8.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 55.000s 27 500 5.40
V2 fifo_levels usbdev_fifo_levels 47.000s 5 160 3.12
V2 rxenable_out_conditional usbdev_rxenable_out 46.000s 0 5 0.00
V2 intr_test usbdev_intr_test 46.000s 0 50 0.00
V2 alert_test usbdev_alert_test 42.000s 3 50 6.00
V2 tl_d_oob_addr_access usbdev_tl_errors 50.000s 1 20 5.00
V2 tl_d_illegal_access usbdev_tl_errors 50.000s 1 20 5.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 42.000s 0 5 0.00
usbdev_csr_rw 38.000s 1 20 5.00
usbdev_csr_aliasing 37.000s 0 5 0.00
usbdev_same_csr_outstanding 46.000s 1 20 5.00
V2 tl_d_partial_access usbdev_csr_hw_reset 42.000s 0 5 0.00
usbdev_csr_rw 38.000s 1 20 5.00
usbdev_csr_aliasing 37.000s 0 5 0.00
usbdev_same_csr_outstanding 46.000s 1 20 5.00
V2 TOTAL 183 3769 4.86
V2S tl_intg_err usbdev_sec_cm 30.000s 0 5 0.00
usbdev_tl_intg_err 38.000s 0 20 0.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 38.000s 0 20 0.00
V2S TOTAL 0 25 0.00
V3 dpi_config_host usbdev_dpi_config_host 38.000s 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests usbdev_stress_all_with_rand_reset 42.000s 0 10 0.00
usbdev_stress_all 42.000s 0 50 0.00
TOTAL 186 3970 4.69

Failure Buckets