CHIP Simulation Results

Tuesday September 16 2025 00:06:28 UTC

GitHub Revision: `996a7b4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	20.245s		0	3	0.00
		chip_sw_example_rom	16.461s		0	3	0.00
		chip_sw_example_manufacturer	19.437s		0	3	0.00
		chip_sw_example_concurrency	18.095s		0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset	5.450m	8.032ms	1	5	20.00
V1	csr_rw	chip_csr_rw	11.383m	5.199ms	2	20	10.00
V1	csr_bit_bash	chip_csr_bit_bash	5.917m	4.651ms	1	5	20.00
V1	csr_aliasing	chip_csr_aliasing	45.000s		0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	12.467m	9.783ms	1	20	5.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	45.000s		0	5	0.00
		chip_csr_rw	11.383m	5.199ms	2	20	10.00
V1	xbar_smoke	xbar_smoke	47.000s		0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	14.886s		0	3	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	14.886s		0	3	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	14.886s		0	3	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.559s		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.559s		0	5	0.00
		chip_sw_uart_tx_rx_idx1	18.693s		0	5	0.00
		chip_sw_uart_tx_rx_idx2	18.087s		0	5	0.00
		chip_sw_uart_tx_rx_idx3	17.817s		0	5	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	47.783m	8.672ms	1	20	5.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.224s		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.030s		0	5	0.00
V1		TOTAL			6	220	2.73
V2	chip_pin_mux	chip_padctrl_attributes	9.200m	6.207ms	3	10	30.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	9.200m	6.207ms	3	10	30.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	18.330s		0	3	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	18.844s		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	18.930s		0	3	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	46.000s		0	5	0.00
		chip_tap_straps_testunlock0	19.625s		0	5	0.00
		chip_tap_straps_rma	22.119s		0	5	0.00
		chip_tap_straps_prod	41.004s		0	5	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	18.093s		0	3	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	19.242s		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	33.000s		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	33.000s		0	6	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	22.329s		0	3	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	16.473s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.467s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	20.728s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	17.214s		0	3	0.00
		chip_sw_aes_enc_jitter_en	16.954s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	18.217s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	19.193s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	25.818s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.254s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.825s		0	3	0.00
		chip_sw_clkmgr_jitter	21.124s		0	3	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	15.149s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	26.000s		0	5	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	16.392s		0	3	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	17.363s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	16.392s		0	3	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	24.357s		0	3	0.00
		chip_sw_aes_smoketest	19.362s		0	3	0.00
		chip_sw_aon_timer_smoketest	18.100s		0	3	0.00
		chip_sw_clkmgr_smoketest	19.896s		0	3	0.00
		chip_sw_csrng_smoketest	18.091s		0	3	0.00
		chip_sw_entropy_src_smoketest	18.750s		0	3	0.00
		chip_sw_gpio_smoketest	19.539s		0	3	0.00
		chip_sw_hmac_smoketest	18.751s		0	3	0.00
		chip_sw_kmac_smoketest	19.597s		0	3	0.00
		chip_sw_otbn_smoketest	19.587s		0	3	0.00
		chip_sw_pwrmgr_smoketest	19.383s		0	3	0.00
		chip_sw_pwrmgr_usbdev_smoketest	17.851s		0	3	0.00
		chip_sw_rv_plic_smoketest	19.546s		0	3	0.00
		chip_sw_rv_timer_smoketest	17.878s		0	3	0.00
		chip_sw_rstmgr_smoketest	19.483s		0	3	0.00
		chip_sw_sram_ctrl_smoketest	20.128s		0	3	0.00
		chip_sw_uart_smoketest	18.374s		0	3	0.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	20.027s		0	3	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	21.520s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	18.574s		0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	23.044s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	20.091s		0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	21.892s		0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	24.414s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	17.757s		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	17.810s		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.817m	2.642ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.817m	2.642ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	45.000s		0	5	0.00
		chip_same_csr_outstanding	37.400m	16.271ms	2	20	10.00
		chip_csr_hw_reset	5.450m	8.032ms	1	5	20.00
		chip_csr_rw	11.383m	5.199ms	2	20	10.00
V2	tl_d_partial_access	chip_csr_aliasing	45.000s		0	5	0.00
		chip_same_csr_outstanding	37.400m	16.271ms	2	20	10.00
		chip_csr_hw_reset	5.450m	8.032ms	1	5	20.00
		chip_csr_rw	11.383m	5.199ms	2	20	10.00
V2	xbar_base_random_sequence	xbar_random	1.117m	2.537ms	0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	55.000s		0	100	0.00
		xbar_smoke_large_delays	1.167m	9.462ms	0	100	0.00
		xbar_smoke_slow_rsp	52.000s	5.241ms	0	100	0.00
		xbar_random_zero_delays	47.000s		0	100	0.00
		xbar_random_large_delays	5.550m	54.605ms	0	100	0.00
		xbar_random_slow_rsp	4.683m	33.290ms	0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	51.000s		0	100	0.00
		xbar_error_and_unmapped_addr	46.000s		0	100	0.00
V2	xbar_error_cases	xbar_error_random	1.017m	2.366ms	0	100	0.00
		xbar_error_and_unmapped_addr	46.000s		0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device	46.000s	1.122ms	0	100	0.00
		xbar_access_same_device_slow_rsp	11.683m	87.466ms	0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	55.000s		0	100	0.00
V2	xbar_stress_all	xbar_stress_all	5.833m	15.537ms	0	100	0.00
		xbar_stress_all_with_error	3.383m	3.609ms	0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.867m	3.632ms	0	100	0.00
		xbar_stress_all_with_reset_error	5.333m	5.493ms	0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	23.044s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	14.908s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	22.027s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	15.511s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	15.822s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	16.599s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	15.718s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	16.176s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	14.213s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	14.213s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	14.213s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	14.758s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.746s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.184s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	14.755s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	15.521s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	14.272s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	14.688s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.175s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	14.666s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.694s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.322s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.075s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.576s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	14.643s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.672s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.677s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.765s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.102s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.215s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.203s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.181s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.638s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	14.906s		0	3	0.00
		rom_e2e_asm_init_dev	22.450s		0	3	0.00
		rom_e2e_asm_init_prod	15.639s		0	3	0.00
		rom_e2e_asm_init_prod_end	21.321s		0	3	0.00
		rom_e2e_asm_init_rma	22.955s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	19.550s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	19.167s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	20.786s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	20.309s		0	3	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	18.079s		0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	18.079s		0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	20.026s		0	3	0.00
		chip_sw_aes_enc_jitter_en	16.954s		0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	19.850s		0	3	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	18.252s		0	3	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	19.036s		0	3	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	18.470s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	18.920s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	23.417m	5.935ms	16	100	16.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	22.080s		0	3	0.00
		chip_plic_all_irqs_10	22.525s		0	3	0.00
		chip_plic_all_irqs_20	46.411s		0	3	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	19.214s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.331s		0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	16.595s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.700m	3.289ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	16.145s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.993s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.435s		0	3	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	17.457s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	18.247s		0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.439s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	19.383s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.439s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	32.066s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	32.066s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	29.000s		0	5	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	34.296s		0	3	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.974s		0	3	0.00
		chip_sw_aes_idle	18.252s		0	3	0.00
		chip_sw_hmac_enc_idle	19.414s		0	3	0.00
		chip_sw_kmac_idle	19.899s		0	3	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	21.754s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	23.188s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	39.123s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	22.884s		0	3	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	24.251s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	22.579s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.037s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	21.843s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	22.702s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	22.701s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	21.697s		0	3	0.00
		chip_sw_ast_clk_outputs	22.329s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	22.316s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	21.843s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	22.702s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.467s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	20.728s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	17.214s		0	3	0.00
		chip_sw_aes_enc_jitter_en	16.954s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	18.217s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	19.193s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	25.818s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.254s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.825s		0	3	0.00
		chip_sw_clkmgr_jitter	21.124s		0	3	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	26.284s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	25.050s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	23.869s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	22.925s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	23.864s		0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	17.093s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	25.169s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	16.766s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	24.100s		0	3	0.00
		chip_sw_flash_init_reduced_freq	25.600s		0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	23.372s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	22.329s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	28.963s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	21.155s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	23.417m	5.935ms	16	100	16.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.993s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	22.148s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	18.470s		0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	20.539s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	19.250s		0	3	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.886h	31.449ms	3	10	30.00
		chip_sw_entropy_src_ast_rng_req	21.718s		0	3	0.00
		chip_sw_edn_entropy_reqs	18.050s		0	3	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	21.718s		0	3	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	22.148s		0	3	0.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	19.546s		0	3	0.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.425s		0	3	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.820s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	20.728s		0	3	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	16.513s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en	18.467s		0	3	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	20.707s		0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.425s		0	3	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	21.386s		0	3	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	20.101s		0	3	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	19.235s		0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	20.707s		0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	19.235s		0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	19.235s		0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	19.235s		0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	19.235s		0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	23.417m	5.935ms	16	100	16.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.817m	11.279ms	1	3	33.33
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	17.872s		0	3	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	17.617s		0	3	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	17.617s		0	3	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	20.941s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	19.193s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	19.414s		0	3	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	18.665s		0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	24.773s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.366s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx1	15.598s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx2	16.795s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	18.089s		0	3	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	20.101s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	25.818s		0	3	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	19.740s		0	3	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	19.036s		0	3	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	24.410s		0	3	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	24.498s		0	3	0.00
		chip_sw_kmac_mode_kmac	23.971s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	20.254s		0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	20.101s		0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	16.986s		0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.402s		0	3	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	19.899s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	18.920s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	46.000s		0	5	0.00
		chip_tap_straps_rma	22.119s		0	5	0.00
		chip_tap_straps_prod	41.004s		0	5	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	20.465s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	19.876s		0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	19.235s		0	3	0.00
		chip_sw_flash_rma_unlocked	20.707s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.274s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.466s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.193s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.648s		0	3	0.00
		chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
		chip_sw_keymgr_key_derivation	20.101s		0	3	0.00
		chip_sw_rom_ctrl_integrity_check	24.573s		0	3	0.00
		chip_sw_sram_ctrl_execution_main	17.632s		0	3	0.00
		chip_prim_tl_access	5.817m	11.279ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_lc	22.316s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	22.579s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.037s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	21.843s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	22.702s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	22.701s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	21.697s		0	3	0.00
		chip_tap_straps_dev	46.000s		0	5	0.00
		chip_tap_straps_rma	22.119s		0	5	0.00
		chip_tap_straps_prod	41.004s		0	5	0.00
		chip_rv_dm_lc_disabled	4.400m	7.961ms	1	3	33.33
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	12.464s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	11.057s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	10.354s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	17.948s		0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.471s		0	3	0.00
		chip_rv_dm_lc_disabled	4.400m	7.961ms	1	3	33.33
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	17.199s		0	3	0.00
		chip_sw_lc_walkthrough_prod	18.357s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	18.763s		0	3	0.00
		chip_sw_lc_walkthrough_rma	16.660s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	18.471s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	23.561s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	24.005s		0	3	0.00
		rom_volatile_raw_unlock	19.632s		0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.133s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	17.214s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	16.974s		0	3	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	16.974s		0	3	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	16.974s		0	3	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	16.531s		0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.425s		0	3	0.00
		chip_sw_otbn_mem_scramble	16.531s		0	3	0.00
		chip_sw_keymgr_key_derivation	20.101s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	23.196s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	18.503s		0	3	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.425s		0	3	0.00
		chip_sw_otbn_mem_scramble	16.531s		0	3	0.00
		chip_sw_keymgr_key_derivation	20.101s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	23.196s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	18.503s		0	3	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	37.884s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	20.465s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.274s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.466s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.193s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.648s		0	3	0.00
		chip_sw_lc_ctrl_transition	17.067m	6.159ms	1	15	6.67
		chip_prim_tl_access	5.817m	11.279ms	1	3	33.33
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.817m	11.279ms	1	3	33.33
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	13.296s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	18.700s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	19.416s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	29.372s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	21.725s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	36.741s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	21.211s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	35.643s		0	3	0.00
		chip_sw_aon_timer_wdog_bite_reset	32.066s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	36.011s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	17.969s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	18.700s		0	3	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	19.147s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	19.012s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	17.809s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	23.570s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.053s		0	3	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.545s		0	3	0.00
		chip_sw_pwrmgr_all_reset_reqs	23.792s		0	3	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	16.787s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	23.098s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	23.417m	5.935ms	16	100	16.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	24.573s		0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	24.573s		0	3	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	23.792s		0	3	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.053s		0	3	0.00
		chip_sw_pwrmgr_wdog_reset	17.969s		0	3	0.00
		chip_sw_pwrmgr_smoketest	19.383s		0	3	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	22.268s		0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.734s		0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	38.309s		0	3	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.331s		0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	39.842s		0	3	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	23.417m	5.935ms	16	100	16.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.435s		0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	19.222s		0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	14.132s		0	3	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	26.242s		0	3	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	18.503s		0	3	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.734s		0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.734s		0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	46.000m	11.146ms	1	3	33.33
V2	chip_jtag_mem_access	chip_jtag_mem_access	54.467m	13.413ms	1	3	33.33
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	22.268s		0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	28.780s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	20.161s		0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	22.119s		0	5	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.400m	7.961ms	1	3	33.33
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.080s		0	3	0.00
		chip_plic_all_irqs_10	22.525s		0	3	0.00
		chip_plic_all_irqs_20	46.411s		0	3	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	22.137s		0	3	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	18.058s		0	3	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	23.044s		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.653s		0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	14.831s		0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	15.572s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	17.702s		0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	23.196s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.825s		0	3	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	17.850s		0	3	0.00
		chip_sw_sleep_sram_ret_contents_scramble	22.627s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.632s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	23.417m	5.935ms	16	100	16.00
		chip_sw_data_integrity_escalation	33.000s		0	6	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.545s		0	3	0.00
		chip_sw_sysrst_ctrl_reset	21.916s		0	3	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	16.192s		0	3	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	22.541s		0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	22.657s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	21.916s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	21.916s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	34.939s		0	3	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	34.939s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	23.454s		0	3	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	18.079s		0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	11.379s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	11.204s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	10.624s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.028s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	10.091s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	9.604s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	11.427s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	9.701s		0	1	0.00
V2		TOTAL			29	2657	1.09
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	18.325s		0	3	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	35.872s		0	3	0.00
V2S		TOTAL			0	6	0.00
V3	chip_sw_coremark	chip_sw_coremark	14.706s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	23.906s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.011s		0	1	0.00
		rom_e2e_jtag_debug_dev	19.551s		0	1	0.00
		rom_e2e_jtag_debug_rma	19.478s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	19.037s		0	1	0.00
		rom_e2e_jtag_inject_dev	22.353s		0	1	0.00
		rom_e2e_jtag_inject_rma	20.869s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	20.456s		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	22.747s		0	3	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	22.307s		0	3	0.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	22.656s		0	3	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	21.198s		0	3	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	21.752s		0	3	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.438s		0	3	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.402s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.516s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	21.312s		0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	28.299s		0	3	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	23.792s		0	3	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.011s		0	1	0.00
		rom_e2e_jtag_debug_dev	19.551s		0	1	0.00
		rom_e2e_jtag_debug_rma	19.478s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	35.418s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	23.417m	5.935ms	16	100	16.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	22.714s		0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	22.714s		0	3	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	15.224s		0	3	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	18.559s		0	5	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	9.709s		0	1	0.00
V3		TOTAL			0	51	0.00
	Unmapped tests	chip_sival_flash_info_access	18.358s		0	3	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	17.986s		0	3	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	17.279s		0	3	0.00
		chip_sw_otp_ctrl_descrambling	18.228s		0	3	0.00
		chip_sw_pwrmgr_lowpower_cancel	28.794s		0	3	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	19.469s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	17.426s		0	3	0.00
		TOTAL			35	2955	1.18

Failure Buckets

Job returned non-zero exit code has 2745 failures:

Test chip_csr_bit_bash has 4 failures.

0.chip_csr_bit_bash.83118589398310859969821961496171870573487893459685543424465942612674714485504
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_bit_bash/latest/run.log

  Trying to check out license...
      Xcelium_Single_Core 24.00 - Failed
      Xcelium_Safety_Sim 24.00 - Failed
      Xcelium_Safety 24.00 - Failed
      Xcelium_Multi_Core 24.00 - Failed
      Xcelium_For_Partners 24.00 - Failed
  xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
  TOOL:	xrun(64)	24.03-s007: Exiting on Sep 16, 2025 at 07:14:16 UTC  (total: 00:00:32)
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2

1.chip_csr_bit_bash.43038950246959502701889338118283387613247077433725161011696813301192595778759
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_csr_bit_bash/latest/run.log

  Trying to check out license...
      Xcelium_Single_Core 24.00 - Failed
      Xcelium_Safety_Sim 24.00 - Failed
      Xcelium_Safety 24.00 - Failed
      Xcelium_Multi_Core 24.00 - Failed
      Xcelium_For_Partners 24.00 - Failed
  xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
  TOOL:	xrun(64)	24.03-s007: Exiting on Sep 16, 2025 at 07:14:23 UTC  (total: 00:00:34)
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2

... and 2 more failures.

Test chip_csr_aliasing has 5 failures.

0.chip_csr_aliasing.100904405302500571441265980358370167034854190978683985904740865619258293777604
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_aliasing/latest/run.log

  Trying to check out license...
      Xcelium_Single_Core 24.00 - Failed
      Xcelium_Safety_Sim 24.00 - Failed
      Xcelium_Safety 24.00 - Failed
      Xcelium_Multi_Core 24.00 - Failed
      Xcelium_For_Partners 24.00 - Failed
  xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
  TOOL:	xrun(64)	24.03-s007: Exiting on Sep 16, 2025 at 07:14:29 UTC  (total: 00:00:45)
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2

1.chip_csr_aliasing.99385744811883912517306509582057794525687176989467701141207399814965760558655
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_csr_aliasing/latest/run.log

  Trying to check out license...
      Xcelium_Single_Core 24.00 - Failed
      Xcelium_Safety_Sim 24.00 - Failed
      Xcelium_Safety 24.00 - Failed
      Xcelium_Multi_Core 24.00 - Failed
      Xcelium_For_Partners 24.00 - Failed
  xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
  TOOL:	xrun(64)	24.03-s007: Exiting on Sep 16, 2025 at 07:14:09 UTC  (total: 00:00:20)
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2

... and 3 more failures.

Test chip_same_csr_outstanding has 18 failures.

0.chip_same_csr_outstanding.2235325908256609651702882074520170753771652423244042479570635712498866140904
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_same_csr_outstanding/latest/run.log

  Trying to check out license...
      Xcelium_Single_Core 24.00 - Failed
      Xcelium_Safety_Sim 24.00 - Failed
      Xcelium_Safety 24.00 - Failed
      Xcelium_Multi_Core 24.00 - Failed
      Xcelium_For_Partners 24.00 - Failed
  xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
  TOOL:	xrun(64)	24.03-s007: Exiting on Sep 16, 2025 at 07:14:20 UTC  (total: 00:00:36)
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2

1.chip_same_csr_outstanding.85209536442738477761380377344665749983289749105056694313246769316544943544796
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_same_csr_outstanding/latest/run.log

  Trying to check out license...
      Xcelium_Single_Core 24.00 - Failed
      Xcelium_Safety_Sim 24.00 - Failed
      Xcelium_Safety 24.00 - Failed
      Xcelium_Multi_Core 24.00 - Failed
      Xcelium_For_Partners 24.00 - Failed
  xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
  TOOL:	xrun(64)	24.03-s007: Exiting on Sep 16, 2025 at 07:14:23 UTC  (total: 00:00:34)
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2

... and 16 more failures.

Test chip_sw_example_flash has 3 failures.

0.chip_sw_example_flash.2977402504789086152126930174023244128177396725121525939328384935081555320418
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_example_flash/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp5332449452134566077/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp5332449452134566077/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp5332449452134566077/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1748:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:example_test_from_flash_sim_dv' failed; build aborted
  INFO: Elapsed time: 4.691s, Critical Path: 0.34s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_flash.64391208285351884614095334326360401903152147021094951380458723042266962800879
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_example_flash/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://deb.debian.org/debian/pool/main/o/openocd/openocd_0.12.0.orig.tar.bz2, https://sourceforge.net/projects/openocd/files/openocd/0.12.0/openocd-0.12.0.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+openocd+openocd/temp17646448281801123954/openocd_0.12.0.orig.tar.bz2: Unknown host: sourceforge.net
  ERROR: no such package '@@+openocd+openocd//': java.io.IOException: Error downloading [https://deb.debian.org/debian/pool/main/o/openocd/openocd_0.12.0.orig.tar.bz2, https://sourceforge.net/projects/openocd/files/openocd/0.12.0/openocd-0.12.0.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+openocd+openocd/temp17646448281801123954/openocd_0.12.0.orig.tar.bz2: Unknown host: sourceforge.net
  ERROR: /nightly/current_run/opentitan/third_party/openocd/BUILD:49:15: //third_party/openocd:build_openocd depends on @@+openocd+openocd//:all_srcs in repository @@+openocd+openocd which failed to fetch. no such package '@@+openocd+openocd//': java.io.IOException: Error downloading [https://deb.debian.org/debian/pool/main/o/openocd/openocd_0.12.0.orig.tar.bz2, https://sourceforge.net/projects/openocd/files/openocd/0.12.0/openocd-0.12.0.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+openocd+openocd/temp17646448281801123954/openocd_0.12.0.orig.tar.bz2: Unknown host: sourceforge.net
  ERROR: Analysis of target '//sw/device/tests:example_test_from_flash_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 10.436s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  FAILED:
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_example_rom has 3 failures.

0.chip_sw_example_rom.77436620969196518360528398878557450761326345933765642797006261800635763238946
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_example_rom/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp6428947001132085071/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp6428947001132085071/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp6428947001132085071/platforms-0.0.11.tar.gz: Unknown host: github.com
  ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1758:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted
  INFO: Elapsed time: 4.330s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_rom.13421351970300551715059625983209561022652856497319451211096568520076047739080
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_example_rom/latest/run.log

          download_info = ctx.download_and_extract(
  Error in download_and_extract: java.io.IOException: Error downloading [https://static.crates.io/crates/bindgen-cli/bindgen-cli-0.71.1.crate] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust_bindgen++rust_ext+rules_rust_bindgen__bindgen-cli-0.71.1/temp13631781744961108094/bindgen-cli-0.71.1.crate.tar.gz: Unknown host: static.crates.io
  ERROR: no such package '@@rules_rust_bindgen++rust_ext+rules_rust_bindgen__bindgen-cli-0.71.1//': java.io.IOException: Error downloading [https://static.crates.io/crates/bindgen-cli/bindgen-cli-0.71.1.crate] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust_bindgen++rust_ext+rules_rust_bindgen__bindgen-cli-0.71.1/temp13631781744961108094/bindgen-cli-0.71.1.crate.tar.gz: Unknown host: static.crates.io
  ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust_bindgen+/3rdparty/BUILD.bazel:54:6: @@rules_rust_bindgen+//3rdparty:bindgen depends on @@rules_rust_bindgen++rust_ext+rules_rust_bindgen__bindgen-cli-0.71.1//:bindgen-cli in repository @@rules_rust_bindgen++rust_ext+rules_rust_bindgen__bindgen-cli-0.71.1 which failed to fetch. no such package '@@rules_rust_bindgen++rust_ext+rules_rust_bindgen__bindgen-cli-0.71.1//': java.io.IOException: Error downloading [https://static.crates.io/crates/bindgen-cli/bindgen-cli-0.71.1.crate] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust_bindgen++rust_ext+rules_rust_bindgen__bindgen-cli-0.71.1/temp13631781744961108094/bindgen-cli-0.71.1.crate.tar.gz: Unknown host: static.crates.io
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 4.400s, Critical Path: 0.23s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  FAILED:
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 320 more tests.

xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_*/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_*/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database. has 158 failures:

Test xbar_smoke_slow_rsp has 14 failures.

0.xbar_smoke_slow_rsp.37981011752640223032904793552774776290942386022703877778728799187835850570512
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_smoke_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

10.xbar_smoke_slow_rsp.94159744776559005500565073547711039728401670584990806730988282146743632985053
Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/10.xbar_smoke_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

... and 12 more failures.

Test xbar_access_same_device_slow_rsp has 9 failures.

0.xbar_access_same_device_slow_rsp.85888706440552823065568200916695511003708215930782908632628890889800661122061
Line 285, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.xbar_access_same_device_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

16.xbar_access_same_device_slow_rsp.85272328611727507471816472286003645315166030488326778106265936144176255032737
Line 277, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/16.xbar_access_same_device_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

... and 7 more failures.

Test xbar_random_slow_rsp has 11 failures.

1.xbar_random_slow_rsp.94927645680662929988045495197664340191371953338282519252615825257171704906452
Line 257, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_random_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

16.xbar_random_slow_rsp.18398939986890048748858935038128602275633123219420559335108157874856222011728
Line 281, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/16.xbar_random_slow_rsp/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

... and 9 more failures.

Test xbar_stress_all_with_reset_error has 8 failures.

2.xbar_stress_all_with_reset_error.10022257114380236699125182498886453037817082201558363664476328814338865034130
Line 2664, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.xbar_stress_all_with_reset_error/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

3.xbar_stress_all_with_reset_error.111547733759522921265063152311918847394451965102813297873147641501973733985444
Line 1200, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/3.xbar_stress_all_with_reset_error/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

... and 6 more failures.

Test xbar_same_source has 6 failures.

3.xbar_same_source.75043847372783675810351338871799562666828788856637006099807331513209759678168
Line 765, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/3.xbar_same_source/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

15.xbar_same_source.45492000127663096834367324331221593885909660142921691082412164774645785681833
Line 725, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/15.xbar_same_source/latest/run.log

  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
  xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
  xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
  xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.

... and 4 more failures.

... and 13 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 12 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 12 failures.
  - 15.chip_sw_alert_handler_lpg_sleep_mode_alerts.48168259974129905738491063657471272553873589888770223357035589248094093094522
    Line 388, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2705.745106 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2705.745106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.chip_sw_alert_handler_lpg_sleep_mode_alerts.111710321986420600566833172074456567481282419058526904825873899203103330461806
    Line 386, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3288.800670 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3288.800670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@178362) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

1.chip_tl_errors.94956900911386700540902593514723507733416594841217936476811323848865047647056
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2173.644386 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@178362) { a_addr: 'h107e4  a_data: 'h5047edb3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h195e5  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2173.644386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@174661) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

3.chip_csr_mem_rw_with_rand_reset.7929408469297155970879861568520302778859018717546657463662246084189358056967
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/3.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2169.019290 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@174661) { a_addr: 'h10540  a_data: 'hc71fe033  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h1ba3c  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2169.019290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175521) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

10.chip_tl_errors.33771520723844480974726622089591872684278904432550252006909250617173729369837
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/10.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2642.160748 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175521) { a_addr: 'h10424  a_data: 'h5e4db2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h181ea  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2642.160748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@174954) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

13.chip_tl_errors.80279754357751286592276749305595682323314889811603572003682455170993144259276
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/13.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2977.373160 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@174954) { a_addr: 'h1051c  a_data: 'h65eb718c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2c  a_opcode: 'h4  a_user: 'h1ae33  d_param: 'h0  d_source: 'h2c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2977.373160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176042) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

17.chip_tl_errors.58306655030327491913053799835218067683611372653010419117413060550097540781272
Line 207, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/17.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2245.197690 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@176042) { a_addr: 'h105c4  a_data: 'h35e41aee  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h18639  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2245.197690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---