ADC_CTRL Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 50.000s 7 50 14.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 29.000s 0 5 0.00
V1 csr_rw adc_ctrl_csr_rw 47.000s 0 20 0.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 37.000s 0 5 0.00
V1 csr_aliasing adc_ctrl_csr_aliasing 42.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 42.000s 3 20 15.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 47.000s 0 20 0.00
adc_ctrl_csr_aliasing 42.000s 0 5 0.00
V1 TOTAL 10 105 9.52
V2 filters_polled adc_ctrl_filters_polled 9.550m 330.931ms 2 50 4.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 9.750m 337.653ms 3 50 6.00
V2 filters_interrupt adc_ctrl_filters_interrupt 5.083m 169.563ms 3 50 6.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 2.500m 166.361ms 1 50 2.00
V2 filters_wakeup adc_ctrl_filters_wakeup 5.650m 199.025ms 5 50 10.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 6.150m 199.890ms 1 50 2.00
V2 filters_both adc_ctrl_filters_both 15.233m 530.858ms 4 50 8.00
V2 clock_gating adc_ctrl_clock_gating 15.900m 548.857ms 2 50 4.00
V2 poweron_counter adc_ctrl_poweron_counter 46.000s 4 50 8.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.150m 37.561ms 3 50 6.00
V2 fsm_reset adc_ctrl_fsm_reset 42.000s 0 50 0.00
V2 stress_all adc_ctrl_stress_all 9.250m 349.677ms 3 50 6.00
V2 alert_test adc_ctrl_alert_test 46.000s 2 50 4.00
V2 intr_test adc_ctrl_intr_test 47.000s 2 50 4.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 46.000s 1 20 5.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 46.000s 1 20 5.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 29.000s 0 5 0.00
adc_ctrl_csr_rw 47.000s 0 20 0.00
adc_ctrl_csr_aliasing 42.000s 0 5 0.00
adc_ctrl_same_csr_outstanding 39.000s 0 20 0.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 29.000s 0 5 0.00
adc_ctrl_csr_rw 47.000s 0 20 0.00
adc_ctrl_csr_aliasing 42.000s 0 5 0.00
adc_ctrl_same_csr_outstanding 39.000s 0 20 0.00
V2 TOTAL 36 740 4.86
V2S tl_intg_err adc_ctrl_sec_cm 39.000s 0 5 0.00
adc_ctrl_tl_intg_err 38.000s 0 20 0.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 38.000s 0 20 0.00
V2S TOTAL 0 25 0.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 50.000s 1 50 2.00
V3 TOTAL 1 50 2.00
TOTAL 47 920 5.11

Failure Buckets