c47b886| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 29.000s | 0 | 1 | 0.00 | |
| V1 | smoke | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| V1 | csr_hw_reset | aes_csr_hw_reset | 42.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | aes_csr_rw | 47.000s | 1 | 20 | 5.00 | |
| V1 | csr_bit_bash | aes_csr_bit_bash | 37.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 39.000s | 1 | 20 | 5.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 47.000s | 1 | 20 | 5.00 | |
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 3 | 106 | 2.83 | |||
| V2 | algorithm | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_config_error | 47.000s | 3 | 50 | 6.00 | |||
| aes_stress | 42.000s | 2 | 50 | 4.00 | |||
| V2 | key_length | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_config_error | 47.000s | 3 | 50 | 6.00 | |||
| aes_stress | 42.000s | 2 | 50 | 4.00 | |||
| V2 | back2back | aes_stress | 42.000s | 2 | 50 | 4.00 | |
| aes_b2b | 47.000s | 1 | 50 | 2.00 | |||
| V2 | backpressure | aes_stress | 42.000s | 2 | 50 | 4.00 | |
| V2 | multi_message | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_config_error | 47.000s | 3 | 50 | 6.00 | |||
| aes_stress | 42.000s | 2 | 50 | 4.00 | |||
| aes_alert_reset | 42.000s | 1 | 50 | 2.00 | |||
| V2 | failure_test | aes_man_cfg_err | 51.000s | 2 | 50 | 4.00 | |
| aes_config_error | 47.000s | 3 | 50 | 6.00 | |||
| aes_alert_reset | 42.000s | 1 | 50 | 2.00 | |||
| V2 | trigger_clear_test | aes_clear | 47.000s | 6 | 50 | 12.00 | |
| V2 | nist_test_vectors | aes_nist_vectors | 50.000s | 0 | 1 | 0.00 | |
| V2 | reset_recovery | aes_alert_reset | 42.000s | 1 | 50 | 2.00 | |
| V2 | stress | aes_stress | 42.000s | 2 | 50 | 4.00 | |
| V2 | sideload | aes_stress | 42.000s | 2 | 50 | 4.00 | |
| aes_sideload | 51.000s | 4 | 50 | 8.00 | |||
| V2 | deinitialization | aes_deinit | 47.000s | 1 | 50 | 2.00 | |
| V2 | stress_all | aes_stress_all | 38.000s | 1 | 10 | 10.00 | |
| V2 | alert_test | aes_alert_test | 46.000s | 0 | 50 | 0.00 | |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 47.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_illegal_access | aes_tl_errors | 47.000s | 1 | 20 | 5.00 | |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 42.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 47.000s | 1 | 20 | 5.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 43.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 42.000s | 0 | 5 | 0.00 | |
| aes_csr_rw | 47.000s | 1 | 20 | 5.00 | |||
| aes_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |||
| aes_same_csr_outstanding | 43.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 22 | 501 | 4.39 | |||
| V2S | reseeding | aes_reseed | 46.000s | 3 | 50 | 6.00 | |
| V2S | fault_inject | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 34.000s | 2 | 20 | 10.00 | |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 34.000s | 2 | 20 | 10.00 | |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 34.000s | 2 | 20 | 10.00 | |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 34.000s | 2 | 20 | 10.00 | |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 38.000s | 2 | 20 | 10.00 | |
| V2S | tl_intg_err | aes_sec_cm | 46.000s | 0 | 5 | 0.00 | |
| aes_tl_intg_err | 39.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 39.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 42.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 34.000s | 2 | 20 | 10.00 | |
| V2S | sec_cm_main_config_sparse | aes_smoke | 47.000s | 1 | 50 | 2.00 | |
| aes_stress | 42.000s | 2 | 50 | 4.00 | |||
| aes_alert_reset | 42.000s | 1 | 50 | 2.00 | |||
| aes_core_fi | 55.000s | 4 | 70 | 5.71 | |||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 34.000s | 2 | 20 | 10.00 | |
| V2S | sec_cm_aux_config_regwen | aes_readability | 47.000s | 4 | 50 | 8.00 | |
| aes_stress | 42.000s | 2 | 50 | 4.00 | |||
| V2S | sec_cm_key_sideload | aes_stress | 42.000s | 2 | 50 | 4.00 | |
| aes_sideload | 51.000s | 4 | 50 | 8.00 | |||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 47.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 47.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_key_sec_wipe | aes_readability | 47.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 47.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 47.000s | 4 | 50 | 8.00 | |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 42.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_key_masking | aes_stress | 42.000s | 2 | 50 | 4.00 | |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_main_fsm_redun | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 4 | 50 | 8.00 | |||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_ctr_fi | 46.000s | 4 | 50 | 8.00 | |||
| V2S | sec_cm_ctrl_sparse | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 4 | 50 | 8.00 | |||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 42.000s | 1 | 50 | 2.00 | |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 4 | 50 | 8.00 | |||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| aes_ctr_fi | 46.000s | 4 | 50 | 8.00 | |||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_ctr_fi | 46.000s | 4 | 50 | 8.00 | |||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 46.000s | 3 | 50 | 6.00 | |
| aes_control_fi | 54.000s | 8 | 300 | 2.67 | |||
| aes_cipher_fi | 55.000s | 12 | 350 | 3.43 | |||
| V2S | TOTAL | 43 | 985 | 4.37 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 38.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 68 | 1602 | 4.24 |
Job returned non-zero exit code has 1530 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.42266054400741982215310956508406894262970210285414936573113573810082252435131
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_wake_up/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:34 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.75274365252810766467186648421816359767538905075982887414532625818470668737196
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_nist_vectors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:55 UTC (total: 00:00:50)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test aes_deinit has 49 failures.
0.aes_deinit.109095397682505439660247283811260187685291411143940226406107172972725233799313
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:36 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_deinit.25477710160775750216512879260954603331115189664293508334329051660631168355095
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:43 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
Test aes_man_cfg_err has 48 failures.
0.aes_man_cfg_err.60889256226222725563817094598575608064458680412157107108757378740015089065569
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:33 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_man_cfg_err.47772604835900289534634500509193534809957359602150225119984669930893054749223
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:57 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
Test aes_readability has 46 failures.
0.aes_readability.11789498910701433927627198489867123633551843938025024253381517161960881363719
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:41 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.aes_readability.85897221149306787188999325540767209091980006255405581901101715538881493802231
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 06:09:41 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 44 more failures.
... and 27 more tests.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 2 failures:
95.aes_cipher_fi.94426346740386996495764909438639522500532896319806185052407616480817917548920
Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/95.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10022336687 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10022336687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
288.aes_cipher_fi.100373829665351320361814323081344909147467993599655414283636916313655912771330
Line 134, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/288.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10002952078 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10002952078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
8.aes_stress_all_with_rand_reset.73482450178725438069918652501768041185575649526669942113014079114422179374021
Line 542, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 291672590 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 291672590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
263.aes_control_fi.76112781291790852929786106123812768027797206846384279782419432211784060698304
Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/263.aes_control_fi/latest/run.log
Job timed out after 1 minutes