c47b886| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 39.000s | 6 | 50 | 12.00 | |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 42.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | csrng_csr_rw | 51.000s | 1 | 20 | 5.00 | |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 34.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | csrng_csr_aliasing | 33.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 42.000s | 2 | 20 | 10.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 51.000s | 1 | 20 | 5.00 | |
| csrng_csr_aliasing | 33.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 9 | 105 | 8.57 | |||
| V2 | interrupts | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| V2 | alerts | csrng_alert | 50.000s | 30 | 500 | 6.00 | |
| V2 | err | csrng_err | 1.050m | 30 | 500 | 6.00 | |
| V2 | cmds | csrng_cmds | 1.850m | 10.591ms | 1 | 50 | 2.00 |
| V2 | life cycle | csrng_cmds | 1.850m | 10.591ms | 1 | 50 | 2.00 |
| V2 | stress_all | csrng_stress_all | 4.400m | 7.245ms | 2 | 50 | 4.00 |
| V2 | intr_test | csrng_intr_test | 47.000s | 0 | 50 | 0.00 | |
| V2 | alert_test | csrng_alert_test | 46.000s | 4 | 50 | 8.00 | |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 55.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | csrng_tl_errors | 55.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 42.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 51.000s | 1 | 20 | 5.00 | |||
| csrng_csr_aliasing | 33.000s | 0 | 5 | 0.00 | |||
| csrng_same_csr_outstanding | 46.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 42.000s | 0 | 5 | 0.00 | |
| csrng_csr_rw | 51.000s | 1 | 20 | 5.00 | |||
| csrng_csr_aliasing | 33.000s | 0 | 5 | 0.00 | |||
| csrng_same_csr_outstanding | 46.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 76 | 1440 | 5.28 | |||
| V2S | tl_intg_err | csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |
| csrng_tl_intg_err | 42.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_config_regwen | csrng_regwen | 55.000s | 1 | 50 | 2.00 | |
| csrng_csr_rw | 51.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_config_mubi | csrng_alert | 50.000s | 30 | 500 | 6.00 | |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 4.400m | 7.245ms | 2 | 50 | 4.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 50.000s | 30 | 500 | 6.00 | |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 4.400m | 7.245ms | 2 | 50 | 4.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 50.000s | 30 | 500 | 6.00 | |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 42.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| csrng_sec_cm | 37.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 55.000s | 9 | 200 | 4.50 | |
| csrng_err | 1.050m | 30 | 500 | 6.00 | |||
| V2S | TOTAL | 3 | 75 | 4.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 34.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 88 | 1630 | 5.40 |
Job returned non-zero exit code has 1533 failures:
0.csrng_smoke.65829667439348614921735452065683279757104814236642955092016494118655097031733
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:38 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_smoke.78539866582091734725647091013745589475959256320073913329535746716406427997760
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:28 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 42 more failures.
0.csrng_stress_all.18738094084312267448469221825190154022790179202438683632175263945774540677819
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:21 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_stress_all.82407054473803971941483305384419126567261651645093915480376776726057905814145
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:36 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 46 more failures.
0.csrng_intr.80055908157296355834474239864585061126213555380526622489398452240536631003359
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:32 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_intr.10358924394134794501862592363015246298926594405212287480401672660443014354673
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_intr/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:36 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 186 more failures.
0.csrng_alert.15949166951954302430062301875593762574075122631884995353870831351244073379720
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:24 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_alert.51990266980869735615330366565051949873771734054069781657479748096117865674327
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:37 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 468 more failures.
0.csrng_regwen.46005071410224533361595611805997932710899202959687067769876797470922980196452
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_regwen/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:24 UTC (total: 00:00:20)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.csrng_regwen.73097393665463519862378190695975769328930714317813545103502532810237188243236
Log /nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_regwen/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:21:42 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_err_vseq] has 3 failures:
6.csrng_err.66224199957050218262625006044893711537107031437442654444520439041504570464550
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/6.csrng_err/latest/run.log
UVM_FATAL @ 1667505 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 1667505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
250.csrng_err.45595885911912469795318668695441318141936732305530426008012050457578228941164
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/250.csrng_err/latest/run.log
UVM_FATAL @ 2128883 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 2128883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 2 failures:
4.csrng_intr.19097167430866827972719212334251969597075408374646022284466615786128911104830
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/4.csrng_intr/latest/run.log
UVM_FATAL @ 121755202 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
----| PATH NOT FOUND
UVM_INFO @ 121755202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
160.csrng_intr.102417722683834473005198001300814032023366228591623582106720827420646793384995
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/160.csrng_intr/latest/run.log
UVM_FATAL @ 126466195 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
----| PATH NOT FOUND
UVM_INFO @ 126466195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 2 failures:
353.csrng_err.24351219103079064031293709042104815518366662722554657920715267060383994745220
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/353.csrng_err/latest/run.log
UVM_FATAL @ 4326586 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 4326586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
461.csrng_err.39111855203568863176108199839706207375298917252562841470741894878077971143830
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/461.csrng_err/latest/run.log
UVM_FATAL @ 1720513 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
----| PATH NOT FOUND
UVM_INFO @ 1720513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,515): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:
37.csrng_intr.16904068557811158959232825466088884576324774450716062163730970949354101380727
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/37.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,515): (time 65433278 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 65433278 ps: (csrng_cmd_stage.sv:515) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 65433278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
140.csrng_err.85204805124769941422899290108773865104107669965069038226479684416005258854523
Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/140.csrng_err/latest/run.log
UVM_ERROR @ 49009687 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
UVM_INFO @ 49009687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---