ENTROPY_SRC/RNG_4BITS Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 46.000s 3 50 6.00
V1 csr_hw_reset entropy_src_csr_hw_reset 30.000s 0 5 0.00
V1 csr_rw entropy_src_csr_rw 50.000s 0 20 0.00
V1 csr_bit_bash entropy_src_csr_bit_bash 29.000s 0 5 0.00
V1 csr_aliasing entropy_src_csr_aliasing 38.000s 1 5 20.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 42.000s 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 50.000s 0 20 0.00
entropy_src_csr_aliasing 38.000s 1 5 20.00
V1 TOTAL 4 105 3.81
V2 firmware entropy_src_smoke 46.000s 3 50 6.00
entropy_src_rng 4.000m 18.062ms 14 300 4.67
entropy_src_fw_ov 3.567m 14.751ms 10 300 3.33
V2 firmware_mode entropy_src_fw_ov 3.567m 14.751ms 10 300 3.33
V2 rng_mode entropy_src_rng 4.000m 18.062ms 14 300 4.67
V2 rng_max_rate entropy_src_rng_max_rate 6.083m 14.023ms 18 400 4.50
V2 health_checks entropy_src_rng 4.000m 18.062ms 14 300 4.67
V2 conditioning entropy_src_rng 4.000m 18.062ms 14 300 4.67
V2 interrupts entropy_src_rng 4.000m 18.062ms 14 300 4.67
entropy_src_intr 46.000s 0 50 0.00
V2 alerts entropy_src_rng 4.000m 18.062ms 14 300 4.67
entropy_src_functional_alerts 43.000s 7 50 14.00
V2 stress_all entropy_src_stress_all 1.783m 9.255ms 5 50 10.00
V2 functional_errors entropy_src_functional_errors 54.000s 57 1000 5.70
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 42.000s 4 50 8.00
V2 intr_test entropy_src_intr_test 47.000s 0 50 0.00
V2 alert_test entropy_src_alert_test 43.000s 1 50 2.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 47.000s 3 20 15.00
V2 tl_d_illegal_access entropy_src_tl_errors 47.000s 3 20 15.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 30.000s 0 5 0.00
entropy_src_csr_rw 50.000s 0 20 0.00
entropy_src_csr_aliasing 38.000s 1 5 20.00
entropy_src_same_csr_outstanding 42.000s 1 20 5.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 30.000s 0 5 0.00
entropy_src_csr_rw 50.000s 0 20 0.00
entropy_src_csr_aliasing 38.000s 1 5 20.00
entropy_src_same_csr_outstanding 42.000s 1 20 5.00
V2 TOTAL 120 2340 5.13
V2S tl_intg_err entropy_src_sec_cm 42.000s 0 5 0.00
entropy_src_tl_intg_err 47.000s 0 20 0.00
V2S sec_cm_config_regwen entropy_src_rng 4.000m 18.062ms 14 300 4.67
entropy_src_cfg_regwen 50.000s 4 50 8.00
V2S sec_cm_config_mubi entropy_src_rng 4.000m 18.062ms 14 300 4.67
V2S sec_cm_config_redun entropy_src_rng 4.000m 18.062ms 14 300 4.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.000m 18.062ms 14 300 4.67
entropy_src_fw_ov 3.567m 14.751ms 10 300 3.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 54.000s 57 1000 5.70
entropy_src_sec_cm 42.000s 0 5 0.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 54.000s 57 1000 5.70
entropy_src_sec_cm 42.000s 0 5 0.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.000m 18.062ms 14 300 4.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 54.000s 57 1000 5.70
entropy_src_sec_cm 42.000s 0 5 0.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 54.000s 57 1000 5.70
entropy_src_sec_cm 42.000s 0 5 0.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 54.000s 57 1000 5.70
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 43.000s 7 50 14.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 47.000s 0 20 0.00
V2S TOTAL 4 75 5.33
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.283m 19.080ms 4 50 8.00
V3 TOTAL 4 50 8.00
TOTAL 132 2570 5.14

Failure Buckets