HMAC Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 38.000s 0 10 0.00
V1 csr_hw_reset hmac_csr_hw_reset 38.000s 0 5 0.00
V1 csr_rw hmac_csr_rw 43.000s 1 20 5.00
V1 csr_bit_bash hmac_csr_bit_bash 30.000s 0 5 0.00
V1 csr_aliasing hmac_csr_aliasing 47.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 46.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 43.000s 1 20 5.00
hmac_csr_aliasing 47.000s 0 5 0.00
V1 TOTAL 2 65 3.08
V2 long_msg hmac_long_msg 51.000s 0 10 0.00
V2 back_pressure hmac_back_pressure 1.067m 1.723ms 2 25 8.00
V2 test_vectors hmac_test_sha256_vectors 3.000m 6.695ms 2 30 6.67
hmac_test_sha384_vectors 6.617m 90.647ms 3 75 4.00
hmac_test_sha512_vectors 46.000s 3 75 4.00
hmac_test_hmac256_vectors 46.000s 2 50 4.00
hmac_test_hmac384_vectors 47.000s 4 60 6.67
hmac_test_hmac512_vectors 47.000s 4 75 5.33
V2 burst_wr hmac_burst_wr 51.000s 1 50 2.00
V2 datapath_stress hmac_datapath_stress 37.000s 0 10 0.00
V2 error hmac_error 38.000s 0 10 0.00
V2 wipe_secret hmac_wipe_secret 38.000s 0 10 0.00
V2 save_and_restore hmac_smoke 38.000s 0 10 0.00
hmac_long_msg 51.000s 0 10 0.00
hmac_back_pressure 1.067m 1.723ms 2 25 8.00
hmac_datapath_stress 37.000s 0 10 0.00
hmac_burst_wr 51.000s 1 50 2.00
hmac_stress_all 7.183m 208.807ms 5 50 10.00
V2 fifo_empty_status_interrupt hmac_smoke 38.000s 0 10 0.00
hmac_long_msg 51.000s 0 10 0.00
hmac_back_pressure 1.067m 1.723ms 2 25 8.00
hmac_datapath_stress 37.000s 0 10 0.00
hmac_wipe_secret 38.000s 0 10 0.00
hmac_test_sha256_vectors 3.000m 6.695ms 2 30 6.67
hmac_test_sha384_vectors 6.617m 90.647ms 3 75 4.00
hmac_test_sha512_vectors 46.000s 3 75 4.00
hmac_test_hmac256_vectors 46.000s 2 50 4.00
hmac_test_hmac384_vectors 47.000s 4 60 6.67
hmac_test_hmac512_vectors 47.000s 4 75 5.33
V2 wide_digest_configurable_key_length hmac_smoke 38.000s 0 10 0.00
hmac_long_msg 51.000s 0 10 0.00
hmac_back_pressure 1.067m 1.723ms 2 25 8.00
hmac_datapath_stress 37.000s 0 10 0.00
hmac_burst_wr 51.000s 1 50 2.00
hmac_error 38.000s 0 10 0.00
hmac_wipe_secret 38.000s 0 10 0.00
hmac_test_sha256_vectors 3.000m 6.695ms 2 30 6.67
hmac_test_sha384_vectors 6.617m 90.647ms 3 75 4.00
hmac_test_sha512_vectors 46.000s 3 75 4.00
hmac_test_hmac256_vectors 46.000s 2 50 4.00
hmac_test_hmac384_vectors 47.000s 4 60 6.67
hmac_test_hmac512_vectors 47.000s 4 75 5.33
hmac_stress_all 7.183m 208.807ms 5 50 10.00
V2 stress_all hmac_stress_all 7.183m 208.807ms 5 50 10.00
V2 alert_test hmac_alert_test 51.000s 0 50 0.00
V2 intr_test hmac_intr_test 43.000s 3 50 6.00
V2 tl_d_oob_addr_access hmac_tl_errors 42.000s 0 20 0.00
V2 tl_d_illegal_access hmac_tl_errors 42.000s 0 20 0.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 38.000s 0 5 0.00
hmac_csr_rw 43.000s 1 20 5.00
hmac_csr_aliasing 47.000s 0 5 0.00
hmac_same_csr_outstanding 47.000s 0 20 0.00
V2 tl_d_partial_access hmac_csr_hw_reset 38.000s 0 5 0.00
hmac_csr_rw 43.000s 1 20 5.00
hmac_csr_aliasing 47.000s 0 5 0.00
hmac_same_csr_outstanding 47.000s 0 20 0.00
V2 TOTAL 29 670 4.33
V2S tl_intg_err hmac_sec_cm 29.000s 0 5 0.00
hmac_tl_intg_err 46.000s 2 20 10.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 46.000s 2 20 10.00
V2S TOTAL 2 25 8.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 38.000s 0 10 0.00
V3 stress_reset hmac_stress_reset 43.000s 0 25 0.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.017m 12.127ms 3 35 8.57
V3 TOTAL 3 60 5.00
Unmapped tests hmac_directed 20.000s 0 1 0.00
TOTAL 36 821 4.38

Failure Buckets