I2C Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 1.017m 5.639ms 2 50 4.00
V1 target_smoke i2c_target_smoke 50.000s 3 50 6.00
V1 csr_hw_reset i2c_csr_hw_reset 37.000s 0 5 0.00
V1 csr_rw i2c_csr_rw 38.000s 2 20 10.00
V1 csr_bit_bash i2c_csr_bit_bash 34.000s 0 5 0.00
V1 csr_aliasing i2c_csr_aliasing 30.000s 1 5 20.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 42.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 38.000s 2 20 10.00
i2c_csr_aliasing 30.000s 1 5 20.00
V1 TOTAL 9 155 5.81
V2 host_error_intr i2c_host_error_intr 47.000s 0 50 0.00
V2 host_stress_all i2c_host_stress_all 5.233m 10.411ms 0 50 0.00
V2 host_maxperf i2c_host_perf 10.367m 26.407ms 3 50 6.00
V2 host_override i2c_host_override 46.000s 5 50 10.00
V2 host_fifo_watermark i2c_host_fifo_watermark 57.817m 74.756ms 1 50 2.00
V2 host_fifo_overflow i2c_host_fifo_overflow 6.017m 2.161ms 2 50 4.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 46.000s 4 50 8.00
i2c_host_fifo_fmt_empty 42.000s 1 50 2.00
i2c_host_fifo_reset_rx 42.000s 2 50 4.00
V2 host_fifo_full i2c_host_fifo_full 8.800m 3.151ms 2 50 4.00
V2 host_timeout i2c_host_stretch_timeout 42.000s 2 50 4.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 51.000s 3 50 6.00
V2 target_glitch i2c_target_glitch 38.000s 0 2 0.00
V2 target_stress_all i2c_target_stress_all 35.233m 20.545ms 2 50 4.00
V2 target_maxperf i2c_target_perf 38.000s 1 50 2.00
V2 target_fifo_empty i2c_target_stress_rd 43.000s 3 50 6.00
i2c_target_intr_smoke 47.000s 2 50 4.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 50.000s 2 50 4.00
i2c_target_fifo_reset_tx 42.000s 4 50 8.00
V2 target_fifo_full i2c_target_stress_wr 46.000s 2 50 4.00
i2c_target_stress_rd 43.000s 3 50 6.00
i2c_target_intr_stress_wr 26.133m 10.640ms 1 50 2.00
V2 target_timeout i2c_target_timeout 46.000s 1 50 2.00
V2 target_clock_stretch i2c_target_stretch 51.000s 0 50 0.00
V2 bad_address i2c_target_bad_addr 47.000s 3 50 6.00
V2 target_mode_glitch i2c_target_hrst 42.000s 1 50 2.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 51.000s 0 50 0.00
i2c_target_fifo_watermarks_tx 46.000s 0 50 0.00
V2 host_mode_config_perf i2c_host_perf 10.367m 26.407ms 3 50 6.00
i2c_host_perf_precise 46.000s 2 50 4.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 42.000s 2 50 4.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 51.000s 2 50 4.00
V2 target_mode_nack_generation i2c_target_nack_acqfull 46.000s 1 50 2.00
i2c_target_nack_acqfull_addr 42.000s 6 50 12.00
i2c_target_nack_txstretch 55.000s 3 50 6.00
V2 host_mode_halt_on_nak i2c_host_may_nack 50.000s 2 50 4.00
V2 target_mode_smbus_maxlen i2c_target_smbus_maxlen 46.000s 4 50 8.00
V2 alert_test i2c_alert_test 46.000s 1 50 2.00
V2 intr_test i2c_intr_test 46.000s 3 50 6.00
V2 tl_d_oob_addr_access i2c_tl_errors 38.000s 2 20 10.00
V2 tl_d_illegal_access i2c_tl_errors 38.000s 2 20 10.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 37.000s 0 5 0.00
i2c_csr_rw 38.000s 2 20 10.00
i2c_csr_aliasing 30.000s 1 5 20.00
i2c_same_csr_outstanding 38.000s 1 20 5.00
V2 tl_d_partial_access i2c_csr_hw_reset 37.000s 0 5 0.00
i2c_csr_rw 38.000s 2 20 10.00
i2c_csr_aliasing 30.000s 1 5 20.00
i2c_same_csr_outstanding 38.000s 1 20 5.00
V2 TOTAL 74 1792 4.13
V2S tl_intg_err i2c_tl_intg_err 50.000s 1 20 5.00
i2c_sec_cm 34.000s 0 5 0.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 50.000s 1 20 5.00
V2S TOTAL 1 25 4.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 39.000s 0 10 0.00
V3 target_error_intr i2c_target_unexp_stop 43.000s 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 38.000s 0 10 0.00
V3 TOTAL 0 70 0.00
TOTAL 84 2042 4.11

Failure Buckets