KEYMGR Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 42.000s 5 50 10.00
V1 random keymgr_random 46.000s 5 50 10.00
V1 csr_hw_reset keymgr_csr_hw_reset 34.000s 0 5 0.00
V1 csr_rw keymgr_csr_rw 47.000s 1 20 5.00
V1 csr_bit_bash keymgr_csr_bit_bash 42.000s 0 5 0.00
V1 csr_aliasing keymgr_csr_aliasing 38.000s 1 5 20.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 42.000s 1 20 5.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 47.000s 1 20 5.00
keymgr_csr_aliasing 38.000s 1 5 20.00
V1 TOTAL 13 155 8.39
V2 cfgen_during_op keymgr_cfg_regwen 51.000s 7 50 14.00
V2 sideload keymgr_sideload 51.000s 4 50 8.00
keymgr_sideload_kmac 47.000s 4 50 8.00
keymgr_sideload_aes 38.000s 4 50 8.00
keymgr_sideload_otbn 46.000s 1 50 2.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 42.000s 2 50 4.00
V2 lc_disable keymgr_lc_disable 47.000s 8 50 16.00
V2 kmac_error_response keymgr_kmac_rsp_err 54.000s 1 50 2.00
V2 invalid_sw_input keymgr_sw_invalid_input 42.000s 3 50 6.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 42.000s 3 50 6.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 46.000s 2 50 4.00
V2 stress_all keymgr_stress_all 42.000s 3 50 6.00
V2 intr_test keymgr_intr_test 51.000s 2 50 4.00
V2 alert_test keymgr_alert_test 50.000s 5 50 10.00
V2 tl_d_oob_addr_access keymgr_tl_errors 50.000s 0 20 0.00
V2 tl_d_illegal_access keymgr_tl_errors 50.000s 0 20 0.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 34.000s 0 5 0.00
keymgr_csr_rw 47.000s 1 20 5.00
keymgr_csr_aliasing 38.000s 1 5 20.00
keymgr_same_csr_outstanding 51.000s 0 20 0.00
V2 tl_d_partial_access keymgr_csr_hw_reset 34.000s 0 5 0.00
keymgr_csr_rw 47.000s 1 20 5.00
keymgr_csr_aliasing 38.000s 1 5 20.00
keymgr_same_csr_outstanding 51.000s 0 20 0.00
V2 TOTAL 49 740 6.62
V2S sec_cm_additional_check keymgr_sec_cm 38.000s 0 5 0.00
V2S tl_intg_err keymgr_sec_cm 38.000s 0 5 0.00
keymgr_tl_intg_err 55.000s 2 20 10.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 50.000s 2 20 10.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 50.000s 2 20 10.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 50.000s 2 20 10.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 50.000s 2 20 10.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 39.000s 4 20 20.00
V2S prim_count_check keymgr_sec_cm 38.000s 0 5 0.00
V2S prim_fsm_check keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 55.000s 2 20 10.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 50.000s 2 20 10.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 51.000s 7 50 14.00
V2S sec_cm_reseed_config_regwen keymgr_random 46.000s 5 50 10.00
keymgr_csr_rw 47.000s 1 20 5.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 46.000s 5 50 10.00
keymgr_csr_rw 47.000s 1 20 5.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 46.000s 5 50 10.00
keymgr_csr_rw 47.000s 1 20 5.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 47.000s 8 50 16.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 42.000s 3 50 6.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 42.000s 3 50 6.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 46.000s 5 50 10.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 47.000s 6 50 12.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 43.000s 0 50 0.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 47.000s 8 50 16.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 43.000s 0 50 0.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 43.000s 0 50 0.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 43.000s 0 50 0.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 38.000s 0 5 0.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 43.000s 0 50 0.00
V2S TOTAL 14 165 8.48
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 42.000s 5 50 10.00
V3 TOTAL 5 50 10.00
TOTAL 81 1110 7.30

Failure Buckets