KMAC/UNMASKED Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 50.000s 0 50 0.00
V1 csr_hw_reset kmac_csr_hw_reset 34.000s 0 5 0.00
V1 csr_rw kmac_csr_rw 43.000s 0 20 0.00
V1 csr_bit_bash kmac_csr_bit_bash 29.000s 0 5 0.00
V1 csr_aliasing kmac_csr_aliasing 47.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 47.000s 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 43.000s 0 20 0.00
kmac_csr_aliasing 47.000s 0 5 0.00
V1 mem_walk kmac_mem_walk 29.000s 0 5 0.00
V1 mem_partial_access kmac_mem_partial_access 29.000s 0 5 0.00
V1 TOTAL 0 115 0.00
V2 long_msg_and_output kmac_long_msg_and_output 20.817m 55.462ms 0 50 0.00
V2 burst_write kmac_burst_write 47.000s 0 50 0.00
V2 test_vectors kmac_test_vectors_sha3_224 34.000s 0 5 0.00
kmac_test_vectors_sha3_256 39.000s 0 5 0.00
kmac_test_vectors_sha3_384 42.000s 0 5 0.00
kmac_test_vectors_sha3_512 34.000s 0 5 0.00
kmac_test_vectors_shake_128 35.000s 0 5 0.00
kmac_test_vectors_shake_256 30.000s 0 5 0.00
kmac_test_vectors_kmac 35.000s 0 5 0.00
kmac_test_vectors_kmac_xof 30.000s 0 5 0.00
V2 sideload kmac_sideload 1.333m 6.472ms 0 50 0.00
V2 app kmac_app 43.000s 0 50 0.00
V2 app_with_partial_data kmac_app_with_partial_data 30.000s 0 10 0.00
V2 entropy_refresh kmac_entropy_refresh 1.900m 8.704ms 0 50 0.00
V2 error kmac_error 54.000s 0 50 0.00
V2 key_error kmac_key_error 47.000s 0 50 0.00
V2 sideload_invalid kmac_sideload_invalid 46.000s 0 50 0.00
V2 edn_timeout_error kmac_edn_timeout_error 43.000s 0 20 0.00
V2 entropy_mode_error kmac_entropy_mode_error 42.000s 0 20 0.00
V2 entropy_ready_error kmac_entropy_ready_error 34.000s 0 10 0.00
V2 lc_escalation kmac_lc_escalation 47.000s 0 50 0.00
V2 stress_all kmac_stress_all 19.900m 169.467ms 0 50 0.00
V2 intr_test kmac_intr_test 51.000s 0 50 0.00
V2 alert_test kmac_alert_test 46.000s 0 50 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 43.000s 0 20 0.00
V2 tl_d_illegal_access kmac_tl_errors 43.000s 0 20 0.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 34.000s 0 5 0.00
kmac_csr_rw 43.000s 0 20 0.00
kmac_csr_aliasing 47.000s 0 5 0.00
kmac_same_csr_outstanding 38.000s 0 20 0.00
V2 tl_d_partial_access kmac_csr_hw_reset 34.000s 0 5 0.00
kmac_csr_rw 43.000s 0 20 0.00
kmac_csr_aliasing 47.000s 0 5 0.00
kmac_same_csr_outstanding 38.000s 0 20 0.00
V2 TOTAL 0 740 0.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 47.000s 0 20 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 47.000s 0 20 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 47.000s 0 20 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 47.000s 0 20 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 46.000s 0 20 0.00
V2S tl_intg_err kmac_sec_cm 29.000s 0 5 0.00
kmac_tl_intg_err 46.000s 0 20 0.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 46.000s 0 20 0.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 47.000s 0 50 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 50.000s 0 50 0.00
V2S sec_cm_key_sideload kmac_sideload 1.333m 6.472ms 0 50 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 47.000s 0 20 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 29.000s 0 5 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 29.000s 0 5 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 29.000s 0 5 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 50.000s 0 50 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 47.000s 0 50 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 29.000s 0 5 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 1.617m 70.400ms 0 10 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 50.000s 0 50 0.00
V2S TOTAL 0 75 0.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 52.000s 33.270ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 0 940 0.00

Failure Buckets