c47b886| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 51.000s | 1 | 50 | 2.00 | |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | pattgen_csr_rw | 38.000s | 3 | 20 | 15.00 | |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 43.000s | 1 | 5 | 20.00 | |
| V1 | csr_aliasing | pattgen_csr_aliasing | 37.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 47.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 38.000s | 3 | 20 | 15.00 | |
| pattgen_csr_aliasing | 37.000s | 0 | 5 | 0.00 | |||
| V1 | TOTAL | 5 | 105 | 4.76 | |||
| V2 | perf | pattgen_perf | 48.417m | 600.000ms | 1 | 50 | 2.00 |
| V2 | cnt_rollover | cnt_rollover | 58.000s | 5.481ms | 7 | 50 | 14.00 |
| V2 | error | pattgen_error | 42.000s | 6 | 50 | 12.00 | |
| V2 | stress_all | pattgen_stress_all | 47.000s | 0 | 50 | 0.00 | |
| V2 | alert_test | pattgen_alert_test | 46.000s | 0 | 50 | 0.00 | |
| V2 | intr_test | pattgen_intr_test | 55.000s | 4 | 50 | 8.00 | |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 46.000s | 2 | 20 | 10.00 | |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 46.000s | 2 | 20 | 10.00 | |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| pattgen_csr_rw | 38.000s | 3 | 20 | 15.00 | |||
| pattgen_csr_aliasing | 37.000s | 0 | 5 | 0.00 | |||
| pattgen_same_csr_outstanding | 38.000s | 2 | 20 | 10.00 | |||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 38.000s | 0 | 5 | 0.00 | |
| pattgen_csr_rw | 38.000s | 3 | 20 | 15.00 | |||
| pattgen_csr_aliasing | 37.000s | 0 | 5 | 0.00 | |||
| pattgen_same_csr_outstanding | 38.000s | 2 | 20 | 10.00 | |||
| V2 | TOTAL | 22 | 340 | 6.47 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 51.000s | 2 | 20 | 10.00 | |
| pattgen_sec_cm | 38.000s | 1 | 5 | 20.00 | |||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 51.000s | 2 | 20 | 10.00 | |
| V2S | TOTAL | 3 | 25 | 12.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 47.000s | 0 | 50 | 0.00 | |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 46.000s | 10.012ms | 1 | 50 | 2.00 | |
| TOTAL | 31 | 570 | 5.44 |
Job returned non-zero exit code has 531 failures:
0.pattgen_smoke.4508426686412124011254665466868600446319108829334926317270944746549734972860
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:28 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_smoke.8440205749846605415849835416769962460580938049726773884093806191990001856859
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:41 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
0.pattgen_perf.40146635478225901534073122340336023805470430394498052807514058352149078856349
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:29 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_perf.111639138328424822066727272520115052776396220137822209305596148207696829017294
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:28 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 44 more failures.
0.pattgen_error.65087826998516496000849910844676424534243808693887792812886262701730663419168
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:29 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_error.92363329203362893227205693838614800931315026604234126714262461347811517958999
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_error/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:41 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 42 more failures.
0.pattgen_inactive_level.52976003575317205882459102461129220280639053668252901356158195293101505166484
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:39 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_inactive_level.58115635175323556800738483457771538585036449164916092733196859478664304903387
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 02:20:53 UTC (total: 00:00:37)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.pattgen_tl_errors.102164252887618634566296536327774248850604181109802724902996300259020050672395
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_tl_errors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:04:29 UTC (total: 00:00:33)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.pattgen_tl_errors.89161805048978348097586564014540561273683360665424546564278344195451652834738
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_tl_errors/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:04:26 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 16 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
2.pattgen_perf.25437269494498546125946526646309417770995660667907489091835095111134456160547
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.pattgen_perf.101247785827627600235249468377772122590077448333499115508302280072910155216563
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:946) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
7.pattgen_stress_all_with_rand_reset.6295619996571097469861290155411905845441732977652887702688716482525922096605
Line 118, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1343937898 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1343945130 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1343945130 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1344072792 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
31.pattgen_stress_all_with_rand_reset.82777395990624142010301444888305807784559450676757971549421398783348808575610
Line 243, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4000689681 ps: (cip_base_vseq.sv:946) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 4000707288 ps: (cip_base_vseq.sv:850) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4000707288 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 4000837722 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
30.pattgen_inactive_level.36596712696798749973612800905792370691820465934429554358965064966550292480414
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012013901 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x509c2b50, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10012013901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) has 1 failures:
39.pattgen_inactive_level.75797125657129714846940706672262009001423408639911437843708170622233906828841
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10177341094 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x65e7ff10, Comparison=CompareOpEq, exp_data=0x0, call_count=28)
UVM_INFO @ 10177341094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---