c47b886| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 46.000s | 0 | 2 | 0.00 | |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 34.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 43.000s | 1 | 20 | 5.00 | |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 30.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 29.000s | 1 | 5 | 20.00 | |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 50.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 55.000s | 0 | 20 | 0.00 | |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 46.000s | 0 | 20 | 0.00 | |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 39.000s | 0 | 5 | 0.00 | |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 34.000s | 0 | 2 | 0.00 | |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 38.000s | 0 | 2 | 0.00 | |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 21.000s | 0 | 2 | 0.00 | |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 26.000s | 0 | 2 | 0.00 | |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 34.000s | 1 | 2 | 50.00 | |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 29.000s | 0 | 2 | 0.00 | |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 38.000s | 0 | 2 | 0.00 | |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 30.000s | 0 | 8 | 0.00 | |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 34.000s | 0 | 2 | 0.00 | |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 34.000s | 0 | 2 | 0.00 | |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 28.000s | 306.631us | 1 | 2 | 50.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 21.000s | 0 | 2 | 0.00 | |
| V1 | rom_read_access | rv_dm_rom_read_access | 21.000s | 0 | 2 | 0.00 | |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |
| V1 | csr_rw | rv_dm_csr_rw | 51.000s | 1 | 20 | 5.00 | |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 42.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 42.000s | 0 | 20 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| rv_dm_csr_rw | 51.000s | 1 | 20 | 5.00 | |||
| V1 | mem_walk | rv_dm_mem_walk | 42.000s | 0 | 5 | 0.00 | |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 34.000s | 0 | 5 | 0.00 | |
| V1 | TOTAL | 5 | 180 | 2.78 | |||
| V2 | idcode | rv_dm_smoke | 46.000s | 0 | 2 | 0.00 | |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 29.000s | 0 | 2 | 0.00 | |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 47.000s | 1 | 2 | 50.00 | |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 30.000s | 0 | 2 | 0.00 | |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 34.000s | 0 | 2 | 0.00 | |
| V2 | sba | rv_dm_sba_tl_access | 46.000s | 0 | 20 | 0.00 | |
| rv_dm_delayed_resp_sba_tl_access | 38.000s | 0 | 20 | 0.00 | |||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 6.867m | 300.000ms | 0 | 20 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 43.000s | 0 | 20 | 0.00 | |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 38.000s | 0 | 2 | 0.00 | |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 38.000s | 0 | 2 | 0.00 | |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 38.000s | 1 | 2 | 50.00 | |
| V2 | hart_unavail | rv_dm_hart_unavail | 34.000s | 0 | 5 | 0.00 | |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 21.000s | 0 | 1 | 0.00 | |
| rv_dm_tap_fsm_rand_reset | 34.000s | 0 | 10 | 0.00 | |||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 18.000s | 0 | 1 | 0.00 | |
| V2 | stress_all | rv_dm_stress_all | 43.000s | 2 | 50 | 4.00 | |
| V2 | alert_test | rv_dm_alert_test | 46.000s | 5 | 50 | 10.00 | |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 47.000s | 0 | 20 | 0.00 | |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| rv_dm_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |||
| rv_dm_csr_rw | 51.000s | 1 | 20 | 5.00 | |||
| rv_dm_same_csr_outstanding | 38.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 38.000s | 0 | 5 | 0.00 | |
| rv_dm_csr_hw_reset | 46.000s | 0 | 5 | 0.00 | |||
| rv_dm_csr_rw | 51.000s | 1 | 20 | 5.00 | |||
| rv_dm_same_csr_outstanding | 38.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 9 | 251 | 3.59 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 29.000s | 0 | 5 | 0.00 | |
| rv_dm_tl_intg_err | 39.000s | 1 | 20 | 5.00 | |||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 39.000s | 1 | 20 | 5.00 | |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 38.000s | 0 | 2 | 0.00 | |
| rv_dm_debug_disabled | 34.000s | 0 | 2 | 0.00 | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 38.000s | 0 | 2 | 0.00 | |
| rv_dm_debug_disabled | 34.000s | 0 | 2 | 0.00 | |||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 46.000s | 0 | 2 | 0.00 | |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 39.000s | 1 | 10 | 10.00 | |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 47.000s | 1 | 4 | 25.00 | |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 47.000s | 1 | 4 | 25.00 | |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 39.000s | 1 | 10 | 10.00 | |
| V2S | TOTAL | 3 | 41 | 7.32 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 37.000s | 0 | 10 | 0.00 | |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 30.000s | 0 | 1 | 0.00 | ||
| TOTAL | 17 | 483 | 3.52 |
Job returned non-zero exit code has 462 failures:
Test rv_dm_csr_aliasing has 5 failures.
0.rv_dm_csr_aliasing.55750818708060489413790525602636918149460725997406722191111592639425920028448
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_aliasing/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:09:12 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_csr_aliasing.47036188677861734609263409607980155587436141865257540804606230838265382042002
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_csr_aliasing/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:09:04 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 3 more failures.
Test rv_dm_smoke has 2 failures.
0.rv_dm_smoke.100004804964005285868378756398847377729192725544017381915074392948969274222761
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:10:59 UTC (total: 00:00:22)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_smoke.44495139378812196407122662921705743489547616681946858548277437682446169299390
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:11:43 UTC (total: 00:00:46)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test rv_dm_tap_fsm has 1 failures.
0.rv_dm_tap_fsm.43241515574872410514043896209980444734285704118488380982502448233438376064876
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:10:58 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.
0.rv_dm_jtag_dtm_csr_hw_reset.85245449146922306623553640241690134997914090322483692180700117712504732971073
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:08:56 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_jtag_dtm_csr_hw_reset.115597059870631055418245299732316930400490034093851697394314727453729231701735
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:09:12 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 3 more failures.
Test rv_dm_jtag_dtm_csr_rw has 19 failures.
0.rv_dm_jtag_dtm_csr_rw.81584141134910601050378521386911868820582731284037694961876243020484264715095
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_rw/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:08:52 UTC (total: 00:00:17)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.rv_dm_jtag_dtm_csr_rw.4547009753662366186907741322863394292018386961091181530033418232430290734658
Log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/1.rv_dm_jtag_dtm_csr_rw/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 01:09:13 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 17 more failures.
... and 48 more tests.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.rv_dm_bad_sba_tl_access.27963340019299169941382720931922893325706302011193937462418441143405990474121
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23258) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.rv_dm_tl_errors.68277014009196704609439588978198452808958392890617557559546966065023279018433
Line 86, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/2.rv_dm_tl_errors/latest/run.log
UVM_ERROR @ 102521895 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23258) { a_addr: 'h5f68784 a_data: 'h30d729d9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha8 a_opcode: 'h4 a_user: 'h1a6d7 d_param: 'h0 d_source: 'ha8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 102521895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23748) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.rv_dm_csr_mem_rw_with_rand_reset.76291372704036035591036174123041238567552387852132994185422473224570331945703
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/13.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 23349302 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23748) { a_addr: 'h28644494 a_data: 'h53cbdf04 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h95 a_opcode: 'h4 a_user: 'h190dc d_param: 'h0 d_source: 'h95 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 23349302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23663) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
18.rv_dm_csr_mem_rw_with_rand_reset.115457815658992493752570848941877046540139860130602757874852795378032976967365
Line 87, in log /nightly/current_run/scratch/master/rv_dm-sim-xcelium/18.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 62468191 ps: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@23663) { a_addr: 'hbe7e97e4 a_data: 'h353285f6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h65 a_opcode: 'h4 a_user: 'h1b452 d_param: 'h0 d_source: 'h65 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 62468191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---