SYSRST_CTRL Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 39.000s 2 50 4.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 46.000s 2 50 4.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 30.000s 1 5 20.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 34.000s 0 5 0.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 42.000s 0 5 0.00
V1 csr_rw sysrst_ctrl_csr_rw 43.000s 1 20 5.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 42.000s 76.204ms 1 5 20.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 34.000s 1 5 20.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 39.000s 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 43.000s 1 20 5.00
sysrst_ctrl_csr_aliasing 34.000s 1 5 20.00
V1 TOTAL 8 165 4.85
V2 combo_detect sysrst_ctrl_combo_detect 54.000s 2 50 4.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.433m 79.387ms 5 100 5.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 46.000s 2 50 4.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 46.000s 1 50 2.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 46.000s 1 50 2.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 46.000s 5 50 10.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 46.000s 3 50 6.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 51.000s 3 50 6.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.783m 1.653s 3 50 6.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 34.000s 0 2 0.00
V2 stress_all sysrst_ctrl_stress_all 51.000s 0 50 0.00
V2 alert_test sysrst_ctrl_alert_test 47.000s 2 50 4.00
V2 intr_test sysrst_ctrl_intr_test 47.000s 3 50 6.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 38.000s 0 20 0.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 38.000s 0 20 0.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 42.000s 0 5 0.00
sysrst_ctrl_csr_rw 43.000s 1 20 5.00
sysrst_ctrl_csr_aliasing 34.000s 1 5 20.00
sysrst_ctrl_same_csr_outstanding 38.000s 1 20 5.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 42.000s 0 5 0.00
sysrst_ctrl_csr_rw 43.000s 1 20 5.00
sysrst_ctrl_csr_aliasing 34.000s 1 5 20.00
sysrst_ctrl_same_csr_outstanding 38.000s 1 20 5.00
V2 TOTAL 31 692 4.48
V2S tl_intg_err sysrst_ctrl_sec_cm 38.000s 0 5 0.00
sysrst_ctrl_tl_intg_err 43.000s 1 20 5.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 43.000s 1 20 5.00
V2S TOTAL 1 25 4.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 47.000s 2 50 4.00
V3 TOTAL 2 50 4.00
TOTAL 42 932 4.51

Failure Buckets