c47b886| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 47.000s | 3 | 50 | 6.00 | |
| V1 | csr_hw_reset | uart_csr_hw_reset | 30.000s | 1 | 5 | 20.00 | |
| V1 | csr_rw | uart_csr_rw | 46.000s | 2 | 20 | 10.00 | |
| V1 | csr_bit_bash | uart_csr_bit_bash | 31.000s | 0 | 5 | 0.00 | |
| V1 | csr_aliasing | uart_csr_aliasing | 30.000s | 1 | 5 | 20.00 | |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 46.000s | 2 | 20 | 10.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 46.000s | 2 | 20 | 10.00 | |
| uart_csr_aliasing | 30.000s | 1 | 5 | 20.00 | |||
| V1 | TOTAL | 9 | 105 | 8.57 | |||
| V2 | base_random_seq | uart_tx_rx | 47.000s | 33.506ms | 1 | 50 | 2.00 |
| V2 | parity | uart_smoke | 47.000s | 3 | 50 | 6.00 | |
| uart_tx_rx | 47.000s | 33.506ms | 1 | 50 | 2.00 | ||
| V2 | parity_error | uart_intr | 2.500m | 171.621ms | 4 | 50 | 8.00 |
| uart_rx_parity_err | 47.000s | 1 | 50 | 2.00 | |||
| V2 | watermark | uart_tx_rx | 47.000s | 33.506ms | 1 | 50 | 2.00 |
| uart_intr | 2.500m | 171.621ms | 4 | 50 | 8.00 | ||
| V2 | fifo_full | uart_fifo_full | 55.000s | 3 | 50 | 6.00 | |
| V2 | fifo_overflow | uart_fifo_overflow | 6.700m | 82.309ms | 4 | 50 | 8.00 |
| V2 | fifo_reset | uart_fifo_reset | 5.333m | 88.847ms | 18 | 300 | 6.00 |
| V2 | rx_frame_err | uart_intr | 2.500m | 171.621ms | 4 | 50 | 8.00 |
| V2 | rx_break_err | uart_intr | 2.500m | 171.621ms | 4 | 50 | 8.00 |
| V2 | rx_timeout | uart_intr | 2.500m | 171.621ms | 4 | 50 | 8.00 |
| V2 | perf | uart_perf | 3.133m | 12.815ms | 1 | 50 | 2.00 |
| V2 | sys_loopback | uart_loopback | 39.000s | 3 | 50 | 6.00 | |
| V2 | line_loopback | uart_loopback | 39.000s | 3 | 50 | 6.00 | |
| V2 | rx_noise_filter | uart_noise_filter | 46.000s | 0 | 50 | 0.00 | |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 43.000s | 7 | 50 | 14.00 | |
| V2 | tx_overide | uart_tx_ovrd | 46.000s | 0 | 50 | 0.00 | |
| V2 | rx_oversample | uart_rx_oversample | 42.000s | 1 | 50 | 2.00 | |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 9.817m | 121.317ms | 2 | 50 | 4.00 |
| V2 | stress_all | uart_stress_all | 3.967m | 45.234ms | 3 | 50 | 6.00 |
| V2 | alert_test | uart_alert_test | 47.000s | 4 | 50 | 8.00 | |
| V2 | intr_test | uart_intr_test | 43.000s | 1 | 50 | 2.00 | |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 38.000s | 3 | 20 | 15.00 | |
| V2 | tl_d_illegal_access | uart_tl_errors | 38.000s | 3 | 20 | 15.00 | |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 30.000s | 1 | 5 | 20.00 | |
| uart_csr_rw | 46.000s | 2 | 20 | 10.00 | |||
| uart_csr_aliasing | 30.000s | 1 | 5 | 20.00 | |||
| uart_same_csr_outstanding | 47.000s | 0 | 20 | 0.00 | |||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 30.000s | 1 | 5 | 20.00 | |
| uart_csr_rw | 46.000s | 2 | 20 | 10.00 | |||
| uart_csr_aliasing | 30.000s | 1 | 5 | 20.00 | |||
| uart_same_csr_outstanding | 47.000s | 0 | 20 | 0.00 | |||
| V2 | TOTAL | 56 | 1090 | 5.14 | |||
| V2S | tl_intg_err | uart_sec_cm | 38.000s | 0 | 5 | 0.00 | |
| uart_tl_intg_err | 42.000s | 2 | 20 | 10.00 | |||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 42.000s | 2 | 20 | 10.00 | |
| V2S | TOTAL | 2 | 25 | 8.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 50.000s | 2 | 100 | 2.00 | |
| V3 | TOTAL | 2 | 100 | 2.00 | |||
| TOTAL | 69 | 1320 | 5.23 |
Job returned non-zero exit code has 1245 failures:
0.uart_smoke.101696471488832459025020729632872856638106727943795471234404107606821138194611
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:48 UTC (total: 00:00:33)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_smoke.93245220806460804537644594467810533906933330883163962216174560039038686716841
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_smoke/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:58 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.uart_tx_rx.3534359751962526043269236275585053574033330368610518867873609612785965653903
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tx_rx/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:44 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_tx_rx.99276600332421160376606274481945298023786774129849439029775640936765864462890
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tx_rx/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:46 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 47 more failures.
0.uart_fifo_full.56973658013846523974052566240859497802778714230747161809634723585696341929555
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_full/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:36 UTC (total: 00:00:21)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_fifo_full.97682914427199107726818328475779162604482737510495684982899984024191014166484
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_full/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:55 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 45 more failures.
0.uart_fifo_overflow.10035332592073632895243079423792949771402726486513473802924225836215313616872
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_overflow/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:58 UTC (total: 00:00:42)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_fifo_overflow.111999504763465739121381781048152141420265735711458142841804329269280546730625
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_overflow/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:56 UTC (total: 00:00:30)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 44 more failures.
0.uart_fifo_reset.8025834444595288727530054162134178323141577564304940633657925946769049099063
Log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:54 UTC (total: 00:00:38)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
1.uart_fifo_reset.36631437206986694107326365143273648313724954987192521314680775878433313722322
Log /nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_reset/latest/run.log
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 17, 2025 at 05:42:56 UTC (total: 00:00:29)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
... and 280 more failures.
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 3 failures:
Test uart_stress_all has 1 failures.
0.uart_stress_all.43320948841540948499413302260605052137980221773455683698755563918556268881958
Line 85, in log /nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all/latest/run.log
UVM_ERROR @ 23407024408 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 23407067886 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 23407111364 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (159 [0x9f] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 23447719816 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 23803152466 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
Test uart_noise_filter has 2 failures.
46.uart_noise_filter.33504265434464268650974932433449885847218550300742834606187034319805057238373
Line 92, in log /nightly/current_run/scratch/master/uart-sim-xcelium/46.uart_noise_filter/latest/run.log
UVM_ERROR @ 130878365413 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 130878405413 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 130878445413 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (150 [0x96] vs 223 [0xdf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 131123125413 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 131123125413 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
47.uart_noise_filter.52945611710535798083634651268650757363604456246293194964747353479671654913224
Line 80, in log /nightly/current_run/scratch/master/uart-sim-xcelium/47.uart_noise_filter/latest/run.log
UVM_ERROR @ 610408183 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 610474850 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 610541517 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 610608184 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 610674851 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 1 failures:
3.uart_stress_all_with_rand_reset.10193772175150758209385844809812149085935829044776728864129195935334870682126
Line 138, in log /nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7513457015 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_INFO @ 7644124727 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/873
UVM_INFO @ 7667623039 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 7667873041 ps: (cip_base_vseq.sv:874) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
6.uart_noise_filter.18371285677923207924259502204471101787392267073674661385022039717778405987027
Line 81, in log /nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_noise_filter/latest/run.log
UVM_ERROR @ 2783086419 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2783086419 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 3825275997 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 3835320341 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 3835364785 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
31.uart_noise_filter.40678068410670922561690022816510006434478096037258359304260309147226530945030
Line 83, in log /nightly/current_run/scratch/master/uart-sim-xcelium/31.uart_noise_filter/latest/run.log
UVM_ERROR @ 1477325253 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1477325253 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1477325253 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1504534457 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 7
UVM_ERROR @ 1504544874 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty