CHIP Simulation Results

Wednesday September 17 2025 00:56:50 UTC

GitHub Revision: c47b886

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	30.000s		0	3	0.00
		chip_sw_example_rom	38.000s		0	3	0.00
		chip_sw_example_manufacturer	30.000s		0	3	0.00
		chip_sw_example_concurrency	8.283m	3.205ms	1	3	33.33
V1	csr_hw_reset	chip_csr_hw_reset	34.000s		0	5	0.00
V1	csr_rw	chip_csr_rw	4.917m	4.361ms	3	20	15.00
V1	csr_bit_bash	chip_csr_bit_bash	46.000s		0	5	0.00
V1	csr_aliasing	chip_csr_aliasing	43.000s		0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	55.000s	2.469ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	43.000s		0	5	0.00
		chip_csr_rw	4.917m	4.361ms	3	20	15.00
V1	xbar_smoke	xbar_smoke	47.000s		0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	39.000s		0	3	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	39.000s		0	3	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	39.000s		0	3	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	16.333m	4.232ms	1	5	20.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	16.333m	4.232ms	1	5	20.00
		chip_sw_uart_tx_rx_idx1	43.000s		0	5	0.00
		chip_sw_uart_tx_rx_idx2	25.033m	4.360ms	3	5	60.00
		chip_sw_uart_tx_rx_idx3	39.000s		0	5	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.042h	8.185ms	3	20	15.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.488h	12.923ms	1	5	20.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	47.000s		0	5	0.00
V1		TOTAL			12	220	5.45
V2	chip_pin_mux	chip_padctrl_attributes	30.000s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	30.000s		0	10	0.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	39.000s		0	3	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	26.000s		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	21.000s		0	3	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	38.000s		0	5	0.00
		chip_tap_straps_testunlock0	28.833m	5.352ms	1	5	20.00
		chip_tap_straps_rma	32.200m	6.295ms	1	5	20.00
		chip_tap_straps_prod	33.000s		0	5	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.050m	3.263ms	1	3	33.33
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.000s		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	34.000s		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	34.000s		0	6	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	30.179s		0	3	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	25.000s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	26.000s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	38.300m	5.784ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	30.000s		0	3	0.00
		chip_sw_aes_enc_jitter_en	29.000s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	18.075s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	26.000s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	30.000s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	25.000s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.967m	4.767ms	1	3	33.33
		chip_sw_clkmgr_jitter	6.067m	2.428ms	1	3	33.33
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	29.715s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	29.000s		0	5	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	50.000s		0	3	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	29.000s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	50.000s		0	3	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	25.000s		0	3	0.00
		chip_sw_aes_smoketest	34.000s		0	3	0.00
		chip_sw_aon_timer_smoketest	8.700m	2.733ms	1	3	33.33
		chip_sw_clkmgr_smoketest	3.600m	2.369ms	1	3	33.33
		chip_sw_csrng_smoketest	21.000s		0	3	0.00
		chip_sw_entropy_src_smoketest	45.766s		0	3	0.00
		chip_sw_gpio_smoketest	25.000s		0	3	0.00
		chip_sw_hmac_smoketest	14.183m	3.592ms	1	3	33.33
		chip_sw_kmac_smoketest	38.000s		0	3	0.00
		chip_sw_otbn_smoketest	26.000s		0	3	0.00
		chip_sw_pwrmgr_smoketest	34.000s		0	3	0.00
		chip_sw_pwrmgr_usbdev_smoketest	38.000s		0	3	0.00
		chip_sw_rv_plic_smoketest	26.000s		0	3	0.00
		chip_sw_rv_timer_smoketest	38.000s		0	3	0.00
		chip_sw_rstmgr_smoketest	38.000s		0	3	0.00
		chip_sw_sram_ctrl_smoketest	9.200m	3.051ms	1	3	33.33
		chip_sw_uart_smoketest	7.883m	2.465ms	1	3	33.33
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	9.100m	2.928ms	1	3	33.33
V2	chip_sw_rom_functests	rom_keymgr_functest	38.000s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	38.000s		0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	34.000s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	4.122m		0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.933m	2.953ms	0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	26.000s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	38.000s		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	26.000s		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	47.000s		0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	47.000s		0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	43.000s		0	5	0.00
		chip_same_csr_outstanding	46.000s		0	20	0.00
		chip_csr_hw_reset	34.000s		0	5	0.00
		chip_csr_rw	4.917m	4.361ms	3	20	15.00
V2	tl_d_partial_access	chip_csr_aliasing	43.000s		0	5	0.00
		chip_same_csr_outstanding	46.000s		0	20	0.00
		chip_csr_hw_reset	34.000s		0	5	0.00
		chip_csr_rw	4.917m	4.361ms	3	20	15.00
V2	xbar_base_random_sequence	xbar_random	48.000s	1.792ms	0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	46.000s		0	100	0.00
		xbar_smoke_large_delays	1.250m	10.256ms	0	100	0.00
		xbar_smoke_slow_rsp	1.000m	6.675ms	0	100	0.00
		xbar_random_zero_delays	50.000s		0	100	0.00
		xbar_random_large_delays	5.600m	56.870ms	0	100	0.00
		xbar_random_slow_rsp	4.867m	34.070ms	0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	53.000s	1.419ms	0	100	0.00
		xbar_error_and_unmapped_addr	47.000s		0	100	0.00
V2	xbar_error_cases	xbar_error_random	53.000s	2.217ms	0	100	0.00
		xbar_error_and_unmapped_addr	47.000s		0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.700m	3.164ms	0	100	0.00
		xbar_access_same_device_slow_rsp	10.850m	84.771ms	0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.133m	2.407ms	0	100	0.00
V2	xbar_stress_all	xbar_stress_all	7.400m	15.725ms	0	100	0.00
		xbar_stress_all_with_error	6.117m	12.241ms	0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	8.867m	12.286ms	0	100	0.00
		xbar_stress_all_with_reset_error	2.700m	2.871ms	0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	34.000s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.650m	7.706ms	0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.891h	14.487ms	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.776s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.267s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.238s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16.489s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	14.725s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.752s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.800s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.797s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	15.150s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.664s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	15.207s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.858s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.446s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.688s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.494s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.606s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.224s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.693s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.899s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.831s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	14.063s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	14.150s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.221s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.099s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.820s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	10.665s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	4.622m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.030s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3.807m		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	3.666m		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	3.979m		0	3	0.00
		rom_e2e_asm_init_dev	2.713m		0	3	0.00
		rom_e2e_asm_init_prod	3.889m		0	3	0.00
		rom_e2e_asm_init_prod_end	5.671m		0	3	0.00
		rom_e2e_asm_init_rma	2.634m		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	31.000s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	30.000s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.000s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.000s		0	3	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	35.000s		0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	35.000s		0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	39.000s		0	3	0.00
		chip_sw_aes_enc_jitter_en	29.000s		0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	9.100m	2.853ms	2	3	66.67
V2	chip_sw_aes_idle	chip_sw_aes_idle	30.000s		0	3	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	30.000s		0	3	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.467m	2.403ms	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	26.000s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	24.283m	5.036ms	12	100	12.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	38.017m	5.396ms	2	3	66.67
		chip_plic_all_irqs_10	28.340s		0	3	0.00
		chip_plic_all_irqs_20	34.000s		0	3	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	26.000s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	38.000s		0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	29.000s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.133m	3.176ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	30.000s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	30.000s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.000s		0	3	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	39.000s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	34.000s		0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	29.000s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	34.000s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	29.000s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	34.000s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	34.000s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	34.000s		0	5	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	34.000s		0	3	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	22.000s		0	3	0.00
		chip_sw_aes_idle	30.000s		0	3	0.00
		chip_sw_hmac_enc_idle	30.000s		0	3	0.00
		chip_sw_kmac_idle	26.000s		0	3	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	31.652s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	38.000s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	28.676s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	43.000s		0	3	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	42.000s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	30.178s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.867m	4.877ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	37.000s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	31.498s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	34.000s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	34.000s		0	3	0.00
		chip_sw_ast_clk_outputs	30.179s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.950m	5.527ms	1	3	33.33
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	37.000s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	31.498s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	26.000s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	38.300m	5.784ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq_jitter_en	30.000s		0	3	0.00
		chip_sw_aes_enc_jitter_en	29.000s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	18.075s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	26.000s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	30.000s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	25.000s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.967m	4.767ms	1	3	33.33
		chip_sw_clkmgr_jitter	6.067m	2.428ms	1	3	33.33
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	34.000s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	24.033m	5.040ms	1	3	33.33
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	26.000s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	34.000s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	21.000s		0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	29.000s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	39.000s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	33.000s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	33.000s		0	3	0.00
		chip_sw_flash_init_reduced_freq	34.000s		0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	47.000s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	30.179s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	30.000s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	30.018s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	24.283m	5.036ms	12	100	12.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	30.000s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	22.000s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.883m	3.451ms	1	3	33.33
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	26.517m	4.856ms	1	3	33.33
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	29.000s		0	3	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.618h	26.696ms	2	10	20.00
		chip_sw_entropy_src_ast_rng_req	7.917m	2.779ms	1	3	33.33
		chip_sw_edn_entropy_reqs	23.000s		0	3	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	7.917m	2.779ms	1	3	33.33
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	22.000s		0	3	0.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	18.000s		0	3	0.00
V2	chip_sw_flash_init	chip_sw_flash_init	26.000s		0	3	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.000s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	38.300m	5.784ms	1	3	33.33
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	20.000s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en	26.000s		0	3	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	34.000s		0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	26.000s		0	3	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.550m	3.533ms	1	3	33.33
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	38.000s		0	3	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	21.067m	5.708ms	1	3	33.33
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	34.000s		0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	21.067m	5.708ms	1	3	33.33
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	21.067m	5.708ms	1	3	33.33
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	21.067m	5.708ms	1	3	33.33
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	21.067m	5.708ms	1	3	33.33
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	24.283m	5.036ms	12	100	12.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	29.000s		0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	32.883m	5.238ms	1	3	33.33
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	29.000s		0	3	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	29.000s		0	3	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	26.000s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	26.000s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	30.000s		0	3	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	25.000s		0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	30.000s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	25.000s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx1	30.000s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx2	23.433m	4.913ms	1	3	33.33
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	23.467m	3.982ms	1	3	33.33
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	38.000s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	30.000s		0	3	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	29.000s		0	3	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	30.000s		0	3	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	29.000s		0	3	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	33.000s		0	3	0.00
		chip_sw_kmac_mode_kmac	9.000m	2.293ms	1	3	33.33
		chip_sw_kmac_mode_kmac_jitter_en	25.000s		0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	38.000s		0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	38.000s		0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	34.000s		0	3	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	26.000s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	26.000s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	38.000s		0	5	0.00
		chip_tap_straps_rma	32.200m	6.295ms	1	5	20.00
		chip_tap_straps_prod	33.000s		0	5	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	11.483m	3.101ms	1	3	33.33
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	25.000s		0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	21.067m	5.708ms	1	3	33.33
		chip_sw_flash_rma_unlocked	34.000s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	30.000s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	30.000s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.000s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	38.683m	7.952ms	1	3	33.33
		chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
		chip_sw_keymgr_key_derivation	38.000s		0	3	0.00
		chip_sw_rom_ctrl_integrity_check	43.000s		0	3	0.00
		chip_sw_sram_ctrl_execution_main	18.000s		0	3	0.00
		chip_prim_tl_access	29.000s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.950m	5.527ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	30.178s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.867m	4.877ms	1	3	33.33
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	37.000s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	31.498s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	34.000s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	34.000s		0	3	0.00
		chip_tap_straps_dev	38.000s		0	5	0.00
		chip_tap_straps_rma	32.200m	6.295ms	1	5	20.00
		chip_tap_straps_prod	33.000s		0	5	0.00
		chip_rv_dm_lc_disabled	38.000s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	9.594s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	14.313s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	14.335s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	38.000s		0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	38.000s		0	3	0.00
		chip_rv_dm_lc_disabled	38.000s		0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	2.819h	46.947ms	1	3	33.33
		chip_sw_lc_walkthrough_prod	44.000s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	25.000s		0	3	0.00
		chip_sw_lc_walkthrough_rma	26.000s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	38.000s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	34.000s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	26.000s		0	3	0.00
		rom_volatile_raw_unlock	5.508m		0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	34.000s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	30.000s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	22.000s		0	3	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	22.000s		0	3	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	22.000s		0	3	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	47.000s		0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	26.000s		0	3	0.00
		chip_sw_otbn_mem_scramble	47.000s		0	3	0.00
		chip_sw_keymgr_key_derivation	38.000s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	29.000s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	30.000s		0	3	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	26.000s		0	3	0.00
		chip_sw_otbn_mem_scramble	47.000s		0	3	0.00
		chip_sw_keymgr_key_derivation	38.000s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	29.000s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	30.000s		0	3	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	31.856s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	11.483m	3.101ms	1	3	33.33
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	30.000s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	30.000s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	21.000s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	38.683m	7.952ms	1	3	33.33
		chip_sw_lc_ctrl_transition	42.000s		0	15	0.00
		chip_prim_tl_access	29.000s		0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	29.000s		0	3	0.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	9.474s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	25.000s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	42.000s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	34.000s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	27.200m	8.659ms	2	3	66.67
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	28.417m	6.725ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	26.907s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	25.000s		0	3	0.00
		chip_sw_aon_timer_wdog_bite_reset	34.000s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	22.000s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	25.000s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	25.000s		0	3	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	21.000s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.000s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	22.000s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	34.000s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.343h	23.553ms	1	3	33.33
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.000s		0	3	0.00
		chip_sw_pwrmgr_all_reset_reqs	30.000s		0	3	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	1.395h	24.408ms	2	3	66.67
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.150m	3.453ms	1	3	33.33
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	24.283m	5.036ms	12	100	12.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	43.000s		0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	43.000s		0	3	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	30.000s		0	3	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.343h	23.553ms	1	3	33.33
		chip_sw_pwrmgr_wdog_reset	25.000s		0	3	0.00
		chip_sw_pwrmgr_smoketest	34.000s		0	3	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	19.917m	4.891ms	1	3	33.33
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	26.000s		0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	14.717m	4.272ms	1	3	33.33
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	38.000s		0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	22.000s		0	3	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	24.283m	5.036ms	12	100	12.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.000s		0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	27.783m	5.174ms	1	3	33.33
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	26.000s		0	3	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	9.850m	2.236ms	1	3	33.33
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	30.000s		0	3	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	26.000s		0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	26.000s		0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	39.000s		0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.000s		0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	19.917m	4.891ms	1	3	33.33
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	30.961s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	38.000s		0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	32.200m	6.295ms	1	5	20.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	38.000s		0	3	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	38.017m	5.396ms	2	3	66.67
		chip_plic_all_irqs_10	28.340s		0	3	0.00
		chip_plic_all_irqs_20	34.000s		0	3	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	30.000s		0	3	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	34.000s		0	3	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	34.000s		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	34.000s		0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	39.000s		0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.800m	3.098ms	1	3	33.33
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	26.000s		0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	29.000s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	18.967m	4.767ms	1	3	33.33
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	28.067m	7.255ms	2	3	66.67
		chip_sw_sleep_sram_ret_contents_scramble	30.000s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.000s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	24.283m	5.036ms	12	100	12.00
		chip_sw_data_integrity_escalation	34.000s		0	6	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	22.000s		0	3	0.00
		chip_sw_sysrst_ctrl_reset	26.000s		0	3	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	9.600m	2.791ms	1	3	33.33
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	38.000s		0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	22.000s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	26.000s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	26.000s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	35.000s		0	3	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	35.000s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	31.000s		0	3	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	35.000s		0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	9.504s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	9.612s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.234s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.355s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	9.414s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	9.618s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	9.222s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	9.403s		0	1	0.00
V2		TOTAL			60	2657	2.26
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	14.000s		0	3	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	34.000s		0	3	0.00
V2S		TOTAL			0	6	0.00
V3	chip_sw_coremark	chip_sw_coremark	27.585s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	25.000s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	13.000s		0	1	0.00
		rom_e2e_jtag_debug_dev	30.000s		0	1	0.00
		rom_e2e_jtag_debug_rma	30.000s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	5.872m		0	1	0.00
		rom_e2e_jtag_inject_dev	6.669m		0	1	0.00
		rom_e2e_jtag_inject_rma	8.048m		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	4.147m		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	29.326s		0	3	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	17.617m	3.176ms	1	3	33.33
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	30.000s		0	3	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	18.719s		0	3	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	25.000s		0	3	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.000s		0	3	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	30.000s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.397s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	38.000s		0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	38.000s		0	3	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	30.000s		0	3	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	13.000s		0	1	0.00
		rom_e2e_jtag_debug_dev	30.000s		0	1	0.00
		rom_e2e_jtag_debug_rma	30.000s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	30.436s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	24.283m	5.036ms	12	100	12.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	25.000s		0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	25.000s		0	3	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	42.000s		0	3	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	16.333m	4.232ms	1	5	20.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	9.462s		0	1	0.00
V3		TOTAL			1	51	1.96
	Unmapped tests	chip_sival_flash_info_access	25.000s		0	3	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	23.000s		0	3	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	26.000s		0	3	0.00
		chip_sw_otp_ctrl_descrambling	9.000m	3.307ms	1	3	33.33
		chip_sw_pwrmgr_lowpower_cancel	37.000s		0	3	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	27.998s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	10.233m	3.257ms	1	3	33.33
		TOTAL			75	2955	2.54

Failure Buckets

• Job returned non-zero exit code has 2692 failures:

  • Test chip_csr_bit_bash has 5 failures.

    • 0.chip_csr_bit_bash.95779984538449736301679389072210452731978263189116412166415133127780646864407
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_bit_bash/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:09:38 UTC  (total: 00:00:21)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • 1.chip_csr_bit_bash.37380026377057503724219403052918861553335854142219032484585068356833697754041
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_csr_bit_bash/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:10:07 UTC  (total: 00:00:46)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • ... and 3 more failures.

  • Test chip_csr_aliasing has 5 failures.

    • 0.chip_csr_aliasing.88579180148990312759151032971425244287623616854059907713422177332427752812005
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_csr_aliasing/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:09:38 UTC  (total: 00:00:20)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • 1.chip_csr_aliasing.5963301634092050858944326337841819472320538183803827583915978700602560982203
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_csr_aliasing/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:10:04 UTC  (total: 00:00:42)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • ... and 3 more failures.

  • Test chip_same_csr_outstanding has 20 failures.

    • 0.chip_same_csr_outstanding.15643454155385256504944575875879250681160043970538716590853973251461757669448
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_same_csr_outstanding/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:09:51 UTC  (total: 00:00:34)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • 1.chip_same_csr_outstanding.22864755165893614272640016534150855591666103133725734391477526012873554456508
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_same_csr_outstanding/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:09:52 UTC  (total: 00:00:30)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • ... and 18 more failures.

  • Test chip_sw_example_flash has 3 failures.

    • 0.chip_sw_example_flash.37430995404268259002845949465768314114697127304033960276609745865456403746908
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_example_flash/latest/run.log

        Building SW image "//sw/device/tests:example_test_from_flash_sim_dv".
        Building "//sw/device/tests:example_test_from_flash_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_flash_sim_dv
        Computing main repo mapping:
        Computing main repo mapping:
        Computing main repo mapping:
        WARNING: Download from https://github.com/lowRISC/misc-linters/archive/refs/tags/20250217_01.tar.gz failed: class com.google.devtools.build.lib.bazel.repository.downloader.UnrecoverableHttpException Unknown host: github.com
        WARNING: Download from https://github.com/jwnrt/rules_multitool/archive/refs/tags/temp-fork-0.4.tar.gz failed: class com.google.devtools.build.lib.bazel.repository.downloader.UnrecoverableHttpException Unknown host: github.com
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/rules_go/0.38.1/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

    • 1.chip_sw_example_flash.7961080072680562109338558738307017762126701973641623843686917224923555249636
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_example_flash/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:18:42 UTC  (total: 00:00:30)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • ... and 1 more failures.

  • Test chip_sw_example_rom has 3 failures.

    • 0.chip_sw_example_rom.93783129704535557859442422261877994398781973822315854155795100597529347268069
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_example_rom/latest/run.log

                fi; \
            fi; \
        done;
        Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
        Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
        Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true //sw/device/tests:example_test_from_rom_sim_dv
        Another command (pid=1081693) is running. Waiting for it to complete on the server (server_pid=1031557)...
        Computing main repo mapping:
        ERROR: Error computing the main repository mapping: Error accessing registry https://bcr.bazel.build/: Failed to fetch registry file https://bcr.bazel.build/modules/rules_go/0.38.1/MODULE.bazel: Unknown host: bcr.bazel.build
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 32
      

    • 1.chip_sw_example_rom.89861405536772739517294621617672976643145371383010439179538503867732220683931
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_example_rom/latest/run.log

        Trying to check out license...
            Xcelium_Single_Core 24.00 - Failed
            Xcelium_Safety_Sim 24.00 - Failed
            Xcelium_Safety 24.00 - Failed
            Xcelium_Multi_Core 24.00 - Failed
            Xcelium_For_Partners 24.00 - Failed
        xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03096'.
        TOOL:	xrun(64)	24.03-s007: Exiting on Sep 17, 2025 at 08:18:07 UTC  (total: 00:00:38)
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 2
      

    • ... and 1 more failures.

  • ... and 320 more tests.

• xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_*/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_*/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database. has 169 failures:

  • Test xbar_smoke_zero_delays has 15 failures.

    • 1.xbar_smoke_zero_delays.33847592648263621806788067453645747228155216123504361365858921086523190319780
      Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_smoke_zero_delays/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • 12.xbar_smoke_zero_delays.108448249857948258011901380640479345496415619224407593846894473505083928242066
      Line 248, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/12.xbar_smoke_zero_delays/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • ... and 13 more failures.

  • Test xbar_random_large_delays has 9 failures.

    • 1.xbar_random_large_delays.108848222297307816060305046631901519055654736857853161006809622272388439484285
      Line 277, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_random_large_delays/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • 3.xbar_random_large_delays.21786933029200899608696700391101785702751633045385614016602669148103610822006
      Line 269, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/3.xbar_random_large_delays/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • ... and 7 more failures.

  • Test xbar_stress_all has 11 failures.

    • 1.xbar_stress_all.60842783297724688554912259044405506538722106725697485785564695617561359485999
      Line 966, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_stress_all/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • 16.xbar_stress_all.92816427989850547531496407263218832862089875586148432565711150850359224068007
      Line 711, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/16.xbar_stress_all/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • ... and 9 more failures.

  • Test xbar_stress_all_with_error has 8 failures.

    • 1.xbar_stress_all_with_error.64116976565071332431868502655151915889383633175219358432465912499152103141966
      Line 2068, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.xbar_stress_all_with_error/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • 54.xbar_stress_all_with_error.26420636894923432004053663122446483727497128325606728330914802657248320097312
      Line 781, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/54.xbar_stress_all_with_error/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • ... and 6 more failures.

  • Test xbar_access_same_device has 9 failures.

    • 3.xbar_access_same_device.39368652925371297445188550428024674863306245157114310115254000864473780240299
      Line 261, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/3.xbar_access_same_device/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • 12.xbar_access_same_device.102387778094070181173637323997475250322655248581923900470686857078097657032706
      Line 317, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/12.xbar_access_same_device/latest/run.log

        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__cored' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__cored' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_core_ibex__corei' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_core_ibex__corei' in the same scope was earlier saved to the database.
        xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'rv_dm__sba' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv:20) with the same instance name 'rv_dm__sba' in the same scope was earlier saved to the database.
        xmsim: *W,COVNBT: (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv:282): Name of named block scope "gen_h2d" shall not be suffixed with a redundant "_T" in IMC type-based coverage in subsequent release in default mode. There may be other such named block scopes in the design.
        xmsim: *N,COVRND: The "implicit default" block of randcase construct (/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_uart_agent_0.1/uart_if.sv:57) has been removed, and will no longer be reported. Please review your refinement file rules for randcase containing design unit(s) if they were generated from older version of Xcelium, before applying them on this design.
      

    • ... and 7 more failures.

  • ... and 13 more tests.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 8 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 8 failures.

    • 20.chip_sw_alert_handler_lpg_sleep_mode_alerts.47134060412176205227816880913645604216196776120880449204940392259565888427884
      Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 2850.517545 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
        UVM_INFO @ 2850.517545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 39.chip_sw_alert_handler_lpg_sleep_mode_alerts.6264065881663005988541087183443324341636126877206115763019111767917053949022
      Line 381, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3364.169400 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
        UVM_INFO @ 3364.169400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• Job timed out after * minutes has 5 failures:

  • Test chip_sw_otbn_smoketest has 1 failures.

    • 0.chip_sw_otbn_smoketest.107397450072464372055962555746315642704451637482455295163624488918724416371984
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/0.chip_sw_otbn_smoketest/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_edn_sw_mode has 1 failures.

    • 1.chip_sw_edn_sw_mode.12467896354250237198819653055540557640496803527398199221874920238482780916450
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_edn_sw_mode/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_keymgr_key_derivation_prod has 1 failures.

    • 1.chip_sw_keymgr_key_derivation_prod.33242713324346834531713035599278562638781869727538398265573172476347818927021
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_keymgr_key_derivation_prod/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.

    • 1.chip_sw_csrng_edn_concurrency_reduced_freq.112498361795590121463965184190502059391111332965120553697471195114985593265065
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log

        Job timed out after 480 minutes
      

  • Test chip_jtag_csr_rw has 1 failures.

    • 2.chip_jtag_csr_rw.114483757045723083252508588661315382309936019310462026855763645671893212921285
      Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_jtag_csr_rw/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 2 failures:

  • Test rom_e2e_shutdown_exception_c has 2 failures.

    • 1.rom_e2e_shutdown_exception_c.4766811628157259595589822276174528160760846864499795037515179527872437268673
      Line 564, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.rom_e2e_shutdown_exception_c/latest/run.log

        UVM_ERROR @ 14486.909577 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
        BF" == "OpenTitan:4001-0002-01x0d
        "
        UVM_INFO @ 14486.909577 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.rom_e2e_shutdown_exception_c.98250356639796265793095864726027659118855728863030104635587584774232960511241
      Line 431, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.rom_e2e_shutdown_exception_c/latest/run.log

        UVM_ERROR @ 15166.827587 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
        BF" == "OpenTitan:4001-0002-01x0d
        "
        UVM_INFO @ 15166.827587 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert *! has 1 failures:

  • Test chip_sw_alert_test has 1 failures.

    • 1.chip_sw_alert_test.35763701192456180502454623240165132452481064527706110013049855013735490834600
      Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/1.chip_sw_alert_test/latest/run.log

        UVM_ERROR @ 2403.075088 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert 31!
        UVM_INFO @ 2403.075088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:92) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_idle_load has 1 failures.

    • 2.chip_sw_power_idle_load.43782429260490790266174348493255794193359045410169306675317560247991502556340
      Line 386, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.chip_sw_power_idle_load/latest/run.log

        UVM_ERROR @ 2952.605000 us: (chip_sw_power_idle_load_vseq.sv:92) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 2952.605000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 1 failures:

  • Test rom_e2e_shutdown_output has 1 failures.

    • 2.rom_e2e_shutdown_output.39925472489322985234746264797019289949654660532755929705536708361783692632906
      Line 488, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/2.rom_e2e_shutdown_output/latest/run.log

        UVM_ERROR @ 7706.219857 us: (chip_sw_rom_e2e_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
        BF" == "OpenTitan:4001-0002-01x0d
        "
        UVM_INFO @ 7706.219857 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:556) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175229) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 1 failures.

    • 10.chip_csr_mem_rw_with_rand_reset.31032350215026799781618284940848938043587674341862742714974249511980166537071
      Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-xcelium/10.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2468.960522 us: (cip_base_scoreboard.sv:556) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@175229) { a_addr: 'h10778  a_data: 'hd1cb796d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h199c8  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2468.960522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---