AES/MASKED Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: `371772adfd`

Branch: dj-sw-nightly

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	39.000s	53.433us	1	1	100.00
V1	smoke	aes_smoke	40.000s	93.957us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	57.794us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	65.405us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	2.448ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	414.563us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	151.062us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	65.405us	20	20	100.00
		aes_csr_aliasing	6.000s	414.563us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	40.000s	93.957us	50	50	100.00
		aes_config_error	40.000s	56.061us	50	50	100.00
		aes_stress	47.000s	5.651ms	50	50	100.00
V2	key_length	aes_smoke	40.000s	93.957us	50	50	100.00
		aes_config_error	40.000s	56.061us	50	50	100.00
		aes_stress	47.000s	5.651ms	50	50	100.00
V2	back2back	aes_stress	47.000s	5.651ms	50	50	100.00
		aes_b2b	50.000s	241.970us	50	50	100.00
V2	backpressure	aes_stress	47.000s	5.651ms	50	50	100.00
V2	multi_message	aes_smoke	40.000s	93.957us	50	50	100.00
		aes_config_error	40.000s	56.061us	50	50	100.00
		aes_stress	47.000s	5.651ms	50	50	100.00
		aes_alert_reset	43.000s	1.399ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	40.000s	96.002us	50	50	100.00
		aes_config_error	40.000s	56.061us	50	50	100.00
		aes_alert_reset	43.000s	1.399ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.067m	3.561ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	57.000s	3.227ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	43.000s	1.399ms	50	50	100.00
V2	stress	aes_stress	47.000s	5.651ms	50	50	100.00
V2	sideload	aes_stress	47.000s	5.651ms	50	50	100.00
		aes_sideload	40.000s	148.700us	50	50	100.00
V2	deinitialization	aes_deinit	1.983m	6.180ms	50	50	100.00
V2	stress_all	aes_stress_all	42.000s	224.180us	9	10	90.00
V2	alert_test	aes_alert_test	39.000s	63.842us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	854.627us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	854.627us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	57.794us	5	5	100.00
		aes_csr_rw	5.000s	65.405us	20	20	100.00
		aes_csr_aliasing	6.000s	414.563us	5	5	100.00
		aes_same_csr_outstanding	6.000s	378.287us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	57.794us	5	5	100.00
		aes_csr_rw	5.000s	65.405us	20	20	100.00
		aes_csr_aliasing	6.000s	414.563us	5	5	100.00
		aes_same_csr_outstanding	6.000s	378.287us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	40.000s	87.043us	50	50	100.00
V2S	fault_inject	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_cipher_fi	54.000s	10.004ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	80.053us	9	20	45.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	80.053us	9	20	45.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	80.053us	9	20	45.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	80.053us	9	20	45.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	26.484us	8	20	40.00
V2S	tl_intg_err	aes_sec_cm	42.000s	541.544us	5	5	100.00
		aes_tl_intg_err	7.000s	1.941ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.941ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	43.000s	1.399ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	80.053us	9	20	45.00
V2S	sec_cm_main_config_sparse	aes_smoke	40.000s	93.957us	50	50	100.00
		aes_stress	47.000s	5.651ms	50	50	100.00
		aes_alert_reset	43.000s	1.399ms	50	50	100.00
		aes_core_fi	50.000s	10.007ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	80.053us	9	20	45.00
V2S	sec_cm_aux_config_regwen	aes_readability	39.000s	78.783us	50	50	100.00
		aes_stress	47.000s	5.651ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	47.000s	5.651ms	50	50	100.00
		aes_sideload	40.000s	148.700us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	39.000s	78.783us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	39.000s	78.783us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	39.000s	78.783us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	39.000s	78.783us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	39.000s	78.783us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	47.000s	5.651ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	47.000s	5.651ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	40.000s	155.676us	45	50	90.00
V2S	sec_cm_main_fsm_redun	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_cipher_fi	54.000s	10.004ms	338	350	96.57
		aes_ctr_fi	39.000s	114.886us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	40.000s	155.676us	45	50	90.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_cipher_fi	54.000s	10.004ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	10.004ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	40.000s	155.676us	45	50	90.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_ctr_fi	39.000s	114.886us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_cipher_fi	54.000s	10.004ms	338	350	96.57
		aes_ctr_fi	39.000s	114.886us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	43.000s	1.399ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_cipher_fi	54.000s	10.004ms	338	350	96.57
		aes_ctr_fi	39.000s	114.886us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_cipher_fi	54.000s	10.004ms	338	350	96.57
		aes_ctr_fi	39.000s	114.886us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_ctr_fi	39.000s	114.886us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	40.000s	155.676us	45	50	90.00
		aes_control_fi	50.000s	10.004ms	284	300	94.67
		aes_cipher_fi	54.000s	10.004ms	338	350	96.57
V2S		TOTAL			924	985	93.81
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	50.000s	4.118ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1530	1602	95.51

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.59	96.45	99.41	95.57	98.07	97.04	98.95	98.80

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 27 failures:

Test aes_fi has 5 failures.

0.aes_fi.95462581875210927872367870003486501840965625628098920880382557801446034251081
Line 561, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/0.aes_fi/latest/run.log

  UVM_FATAL @  21101221 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  21101221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_fi.82582848796491583478580258596574982830836771189762308748460293365085986245531
Line 1410, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/2.aes_fi/latest/run.log

  UVM_FATAL @  27967452 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  27967452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aes_shadow_reg_errors_with_csr_rw has 11 failures.

0.aes_shadow_reg_errors_with_csr_rw.57428886906336744263539753086935036431665114585558623133430110572155009851728
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  26484180 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  26484180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_shadow_reg_errors_with_csr_rw.40017406278484636493794645244189239776408649615549209329319410750652195232657
Line 104, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/3.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  43583683 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  43583683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test aes_shadow_reg_errors has 10 failures.

2.aes_shadow_reg_errors.9764169792360023652497424275235158954979709436287144338211186633153272158112
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/2.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @   9059535 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   9059535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_shadow_reg_errors.28341045154305187398383998458557006793309649295537037532218361016656109187240
Line 104, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/5.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @ 130971079 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 130971079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test aes_stress_all has 1 failures.

4.aes_stress_all.111660230693930731351519256765024078577617398173569932455675154254784434564035
Line 115775, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/4.aes_stress_all/latest/run.log

  UVM_FATAL @ 1407793672 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 1407793672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 67.aes_cipher_fi.4594941923781102138924669284719644922285367167553378413501758521286786904491
    Line 133, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/67.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021118003 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021118003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 69.aes_cipher_fi.81171889576803591218746617792266044396116528314491973288875961544958103908942
    Line 140, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/69.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10032257534 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032257534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
Job timed out after * minutes has 9 failures:
- Test aes_control_fi has 9 failures.
  - 8.aes_control_fi.32246439452802436674133241351260495447511342161874419395944324978846241720712
    Log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 38.aes_control_fi.20287299990087558448238603378600451477623948231265763940223907708610455745595
    Log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 3.aes_control_fi.21150554797215296162646664923025934765600866400093275887275711840529478986275
    Line 137, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10030801060 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030801060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 106.aes_control_fi.92938971811138971777279788855129663221998479797226032367093097576255867426595
    Line 145, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/106.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10039625117 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039625117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.34760854482547310076202118082814185157290960388541416014718529370396574240084
Line 200, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 946929490 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 946929490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.60080009179177823469984544712290914687797852056114645150715053168634946282598
Line 428, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3065914903 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3065914903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 14.aes_core_fi.69362387267243687408054773827638181162160115943416787612381685933824288565628
    Line 138, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006527066 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006527066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 40.aes_core_fi.30587652080686162090058288730524951990444185515604250554255248544944310758132
    Line 139, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007494661 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007494661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:891) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.6300471418886775686712595891098860782993937517764700455319315297501666219161
    Line 214, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1763977621 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1763977621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.23468876864016210764090405834130851490648611989801992786314001694105080753923
    Line 216, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 594652331 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 594652331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:980) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 2 failures:
- Test aes_shadow_reg_errors has 1 failures.
  - 10.aes_shadow_reg_errors.5903251366391355780428657098935407262332226649372126218149067950416234195974
    Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/10.aes_shadow_reg_errors/latest/run.log
```
  UVM_ERROR @  29958463 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @  29958463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 14.aes_shadow_reg_errors_with_csr_rw.42659494479988756253721773385583944923707681365941304030245703051257054534102
    Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/14.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  30612760 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @  30612760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:580) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.84666858840822205379373076829372017929104687439821050944721357040015247761797
    Line 129, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  59970514 ps: (cip_base_vseq.sv:580) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  59970514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.60639256264965995546710494833974189584810408624223112577285478812115336601742
    Line 177, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  78336976 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  78336976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.35976708774584450803356017601509326499234302408537348889914244583258112435595
    Line 151, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  67813200 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  67813200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,865): Assertion AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

36.aes_core_fi.2475067961865233822401232382066649925973485095140142201127936945565388941948
Line 137, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/36.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 11849353 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 11838936 PS)
  UVM_ERROR @  11849353 ps: (aes_cipher_core.sv:865) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateKeyExpand
  UVM_INFO @  11849353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_ctr_fi_vseq.sv:59) [aes_ctr_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_ctr_fi has 1 failures.
  - 43.aes_ctr_fi.64841549981658684696467394228242281370680122546778099536854109266838449469441
    Line 133, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/43.aes_ctr_fi/latest/run.log
```
  UVM_FATAL @ 10003685779 ps: (aes_ctr_fi_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.aes_ctr_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003685779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```