AES/UNMASKED Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: `371772adfd`

Branch: dj-sw-nightly

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	53.631us	1	1	100.00
V1	smoke	aes_smoke	6.000s	63.920us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	33.000s	71.979us	5	5	100.00
V1	csr_rw	aes_csr_rw	10.000s	171.174us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	328.558us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	260.986us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	346.997us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	10.000s	171.174us	20	20	100.00
		aes_csr_aliasing	7.000s	260.986us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	63.920us	50	50	100.00
		aes_config_error	8.000s	490.079us	50	50	100.00
		aes_stress	6.000s	99.706us	50	50	100.00
V2	key_length	aes_smoke	6.000s	63.920us	50	50	100.00
		aes_config_error	8.000s	490.079us	50	50	100.00
		aes_stress	6.000s	99.706us	50	50	100.00
V2	back2back	aes_stress	6.000s	99.706us	50	50	100.00
		aes_b2b	9.000s	655.009us	50	50	100.00
V2	backpressure	aes_stress	6.000s	99.706us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	63.920us	50	50	100.00
		aes_config_error	8.000s	490.079us	50	50	100.00
		aes_stress	6.000s	99.706us	50	50	100.00
		aes_alert_reset	6.000s	414.191us	48	50	96.00
V2	failure_test	aes_man_cfg_err	7.000s	237.685us	50	50	100.00
		aes_config_error	8.000s	490.079us	50	50	100.00
		aes_alert_reset	6.000s	414.191us	48	50	96.00
V2	trigger_clear_test	aes_clear	7.000s	123.906us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	183.263us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	414.191us	48	50	96.00
V2	stress	aes_stress	6.000s	99.706us	50	50	100.00
V2	sideload	aes_stress	6.000s	99.706us	50	50	100.00
		aes_sideload	7.000s	443.341us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	118.019us	50	50	100.00
V2	stress_all	aes_stress_all	25.000s	1.650ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	88.753us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	46.000s	109.164us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	46.000s	109.164us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	33.000s	71.979us	5	5	100.00
		aes_csr_rw	10.000s	171.174us	20	20	100.00
		aes_csr_aliasing	7.000s	260.986us	5	5	100.00
		aes_same_csr_outstanding	6.000s	157.067us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	33.000s	71.979us	5	5	100.00
		aes_csr_rw	10.000s	171.174us	20	20	100.00
		aes_csr_aliasing	7.000s	260.986us	5	5	100.00
		aes_same_csr_outstanding	6.000s	157.067us	20	20	100.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	6.000s	189.096us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_cipher_fi	34.000s	10.004ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	39.000s	64.074us	11	20	55.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	39.000s	64.074us	11	20	55.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	39.000s	64.074us	11	20	55.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	39.000s	64.074us	11	20	55.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	36.000s	169.205us	9	20	45.00
V2S	tl_intg_err	aes_sec_cm	16.000s	10.697ms	4	5	80.00
		aes_tl_intg_err	43.000s	232.929us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	43.000s	232.929us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	414.191us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	39.000s	64.074us	11	20	55.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	63.920us	50	50	100.00
		aes_stress	6.000s	99.706us	50	50	100.00
		aes_alert_reset	6.000s	414.191us	48	50	96.00
		aes_core_fi	3.883m	10.008ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	39.000s	64.074us	11	20	55.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	55.468us	50	50	100.00
		aes_stress	6.000s	99.706us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	99.706us	50	50	100.00
		aes_sideload	7.000s	443.341us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	55.468us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	55.468us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	55.468us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	55.468us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	55.468us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	99.706us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	99.706us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	219.225us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_cipher_fi	34.000s	10.004ms	322	350	92.00
		aes_ctr_fi	6.000s	64.528us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	219.225us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_cipher_fi	34.000s	10.004ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	34.000s	10.004ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	219.225us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_ctr_fi	6.000s	64.528us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_cipher_fi	34.000s	10.004ms	322	350	92.00
		aes_ctr_fi	6.000s	64.528us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	414.191us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_cipher_fi	34.000s	10.004ms	322	350	92.00
		aes_ctr_fi	6.000s	64.528us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_cipher_fi	34.000s	10.004ms	322	350	92.00
		aes_ctr_fi	6.000s	64.528us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_ctr_fi	6.000s	64.528us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	219.225us	50	50	100.00
		aes_control_fi	57.000s	200.000ms	274	300	91.33
		aes_cipher_fi	34.000s	10.004ms	322	350	92.00
V2S		TOTAL			904	985	91.78
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	30.000s	2.558ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1508	1602	94.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.34	97.69	94.84	98.76	93.72	98.07	93.33	98.64	98.20

Failure Buckets

Job timed out after * minutes has 29 failures:
- Test aes_control_fi has 16 failures.
  - 5.aes_control_fi.45378215544065379558443281445899781889970243956307908790850498817904011858264
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_control_fi.17186444421988695608526085521155060270382771405389839468980375013209573540606
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 13 failures.
  - 14.aes_cipher_fi.42554921248291314755111163841969595829488256839093468062848505736982546411309
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 27.aes_cipher_fi.81251292376247163802470750365450921419727098812403097512299874462525465200933
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 19 failures:

Test aes_shadow_reg_errors has 9 failures.

0.aes_shadow_reg_errors.106259233628234790664516268713040499794399405631792979236543257751503123563098
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  64073615 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  64073615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_shadow_reg_errors.115720098287739488066867798700357385846927868560900478045973173130577208936129
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/4.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  87237662 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  87237662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aes_shadow_reg_errors_with_csr_rw has 9 failures.

0.aes_shadow_reg_errors_with_csr_rw.108055596592801607549831262373960166358813239880831988694747212343261919740932
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 169205195 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 169205195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_shadow_reg_errors_with_csr_rw.95380143767846972984848797196040144599455884261692444156674388547601001299083
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/4.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  16042529 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  16042529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aes_alert_reset has 1 failures.

14.aes_alert_reset.115209469087173842830997268299928506367469850136275504829979794605855424451378
Line 388, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/14.aes_alert_reset/latest/run.log

  UVM_FATAL @  12561555 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  12561555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_cipher_fi has 15 failures.
  - 37.aes_cipher_fi.11203702594458935333160490303713651169821403295603306828364430785243494779023
    Line 145, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009831313 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009831313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 39.aes_cipher_fi.88149509795270807277701799076852817960764173748359997462816977661594460717209
    Line 141, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018927643 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018927643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 52.aes_control_fi.18821990949144049587115265868880184376333126387218229198650811179375979969055
    Line 140, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002927537 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002927537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 55.aes_control_fi.69127675370791061435960290667371106689731425904094185188919085022976615910022
    Line 135, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003241471 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003241471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.68682900404112354061929890035568601531252419708457834724850028374918777529422
Line 988, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1255174440 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1255174440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.40468736293456098405553191576220722905319821995532903761330514898992617118752
Line 830, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2557916282 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2557916282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (cip_base_vseq.sv:980) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 2 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 2 failures.
  - 5.aes_shadow_reg_errors_with_csr_rw.72270220160106686275056808782972551010962334170736807082081214282690261903141
    Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/5.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 328731076 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 328731076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_shadow_reg_errors_with_csr_rw.5549293982262705049295102720202215504769519162357893263592051734221768784165
    Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/6.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 138924539 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 138924539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 6.aes_core_fi.75899273585150239803841578744835398137815644851397136819869719534355706544861
    Line 143, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10111042253 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10111042253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 58.aes_core_fi.54925188878555220424236311661824058007170005191375806997172037284382514745152
    Line 140, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/58.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010940395 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010940395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:

Test aes_core_fi has 2 failures.

7.aes_core_fi.52609357698218521174455021282440531156702262895221892024797899146608783411525
Line 140, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log

  UVM_FATAL @ 10050365768 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x18724e84, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10050365768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.aes_core_fi.28035199355083740875577323699697902012172704902162700713916232389144257822312
Line 141, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/25.aes_core_fi/latest/run.log

  UVM_FATAL @ 10043665821 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x85590084, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10043665821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:666) [aes_common_vseq] timeout wait for alert handshake:fatal_fault has 1 failures:
- Test aes_sec_cm has 1 failures.
  - 2.aes_sec_cm.101146000918965975003247624933638002726768398023118053483598260717132490457954
    Line 236, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/2.aes_sec_cm/latest/run.log
```
  UVM_FATAL @ 10696765614 ps: (cip_base_vseq.sv:666) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 10696765614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.85064988808620700617210484435154158972744482446892543795016550506290458517453
    Line 163, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 226907257 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 226907257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.60789548090916623177336091275910020614099860100089426260011288878485054864792
    Line 766, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1436112107 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1436112107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:580) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.6295728065020961947608909902612415176598263301200646118335510464877377330617
    Line 6146, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  UVM_ERROR @ 111796379 ps: (cip_base_vseq.sv:580) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 111796379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 13.aes_alert_reset.22973608927712674736149408787201217523458862914315273717686516077644301118565
    Line 406, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/13.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 5556532 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 5546532 PS)
  UVM_ERROR @   5556532 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   5556532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 22.aes_core_fi.50255422711613864242232735496135426523782268343169939007138142591260488928071
    Line 141, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013693004 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013693004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 52.aes_core_fi.63350730873279786695954559938842538520064399492287474381993534803061694399789
    Line 137, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008349172 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x8aec1484, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10008349172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 184.aes_control_fi.57729634430086984995752608126689645945240793146842075479452222671516646511259
    Line 145, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/184.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```