AON_TIMER Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.590s	671.727us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.240s	1.096ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.460s	527.874us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	10.200s	6.964ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.730s	605.333us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.520s	444.186us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.460s	527.874us	20	20	100.00
		aon_timer_csr_aliasing	2.730s	605.333us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.380s	474.350us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.320s	477.084us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	44.090s	41.663ms	15	15	100.00
V2	jump	aon_timer_jump	2.910s	695.061us	5	5	100.00
V2	stress_all	aon_timer_stress_all	1.067m	47.572ms	15	15	100.00
V2	intr_test	aon_timer_intr_test	2.510s	305.192us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.350s	365.157us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.350s	365.157us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.240s	1.096ms	5	5	100.00
		aon_timer_csr_rw	2.460s	527.874us	20	20	100.00
		aon_timer_csr_aliasing	2.730s	605.333us	5	5	100.00
		aon_timer_same_csr_outstanding	5.870s	2.561ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.240s	1.096ms	5	5	100.00
		aon_timer_csr_rw	2.460s	527.874us	20	20	100.00
		aon_timer_csr_aliasing	2.730s	605.333us	5	5	100.00
		aon_timer_same_csr_outstanding	5.870s	2.561ms	20	20	100.00
V2		TOTAL			125	125	100.00
V2S	tl_intg_err	aon_timer_sec_cm	7.530s	3.881ms	5	5	100.00
		aon_timer_tl_intg_err	12.120s	8.204ms	18	20	90.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.120s	8.204ms	18	20	90.00
V2S		TOTAL			23	25	92.00
V3	max_threshold	aon_timer_smoke_max_thold	2.360s	482.583us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	2.100s	513.643us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	7.410s	3.644ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	3.230s	686.919us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	14.870s	4.104ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	40.720s	21.139ms	15	15	100.00
V3		TOTAL			45	45	100.00
	Unmapped tests	aon_timer_alert_test	2.870s	317.947us	50	50	100.00
		TOTAL			313	315	99.37

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:665) [aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault has 2 failures:
  • Test aon_timer_tl_intg_err has 2 failures.

    • 3.aon_timer_tl_intg_err.89189958590237164714345931672257150661532343877869613631023968970820251090040
      Line 133, in log /nightly/runs/scratch/dj-sw-nightly/aon_timer-sim-vcs/3.aon_timer_tl_intg_err/latest/run.log

        UVM_FATAL @ 14110926027 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault
        UVM_INFO @ 14110926027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.aon_timer_tl_intg_err.27184547392213826969927475561412946706676444376554623033601449461636816155515
      Line 118, in log /nightly/runs/scratch/dj-sw-nightly/aon_timer-sim-vcs/10.aon_timer_tl_intg_err/latest/run.log

        UVM_FATAL @ 12205660406 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault
        UVM_INFO @ 12205660406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---