CSRNG Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	24.000s	55.784us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	125.386us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	61.065us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	18.000s	269.251us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	318.344us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	269.856us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	61.065us	20	20	100.00
		csrng_csr_aliasing	12.000s	318.344us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	30.000s	1.477ms	200	200	100.00
V2	alerts	csrng_alert	34.700m	200.000ms	499	500	99.80
V2	err	csrng_err	24.000s	26.899us	499	500	99.80
V2	cmds	csrng_cmds	8.017m	31.061ms	50	50	100.00
V2	life cycle	csrng_cmds	8.017m	31.061ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.167m	142.816ms	46	50	92.00
V2	intr_test	csrng_intr_test	6.000s	167.865us	50	50	100.00
V2	alert_test	csrng_alert_test	22.000s	28.897us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	144.735us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	144.735us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	125.386us	5	5	100.00
		csrng_csr_rw	6.000s	61.065us	20	20	100.00
		csrng_csr_aliasing	12.000s	318.344us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	463.172us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	125.386us	5	5	100.00
		csrng_csr_rw	6.000s	61.065us	20	20	100.00
		csrng_csr_aliasing	12.000s	318.344us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	463.172us	20	20	100.00
V2		TOTAL			1434	1440	99.58
V2S	tl_intg_err	csrng_sec_cm	2.067m	10.410ms	4	5	80.00
		csrng_tl_intg_err	17.000s	748.421us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	24.000s	48.093us	50	50	100.00
		csrng_csr_rw	6.000s	61.065us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	34.700m	200.000ms	499	500	99.80
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.167m	142.816ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_ctrl_mubi	csrng_alert	34.700m	200.000ms	499	500	99.80
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.167m	142.816ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	34.700m	200.000ms	499	500	99.80
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	748.421us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
		csrng_sec_cm	2.067m	10.410ms	4	5	80.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	30.000s	1.477ms	200	200	100.00
		csrng_err	24.000s	26.899us	499	500	99.80
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.983m	6.380ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.75	98.61	96.62	99.94	97.30	92.08	100.00	97.35	90.86

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:

  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.77656400194211812142583681145975714570209913568003019679394207072763407249648
      Line 112, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3485173884 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3485173884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.6767011535309041632032343789416180391072375333789284568090086771673992123014
      Line 109, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 760600851 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 760600851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:

  • Test csrng_stress_all has 4 failures.

    • 6.csrng_stress_all.99682125551486852041394654573301783603058925180426398470915879862457648862656
      Line 151, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log

        UVM_ERROR @ 7070930559 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 7070930559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.csrng_stress_all.60388017806065022013927731070805300422162316322900673544414133315082503585905
      Line 143, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log

        UVM_ERROR @ 27296324955 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 27296324955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_FATAL (cip_base_vseq.sv:666) [csrng_common_vseq] timeout wait for alert handshake:fatal_alert has 1 failures:

  • Test csrng_sec_cm has 1 failures.

    • 2.csrng_sec_cm.10445922256001245024459456934960264547926741174305072550329161983638560499730
      Line 163, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/2.csrng_sec_cm/latest/run.log

        UVM_FATAL @ 10410151602 ps: (cip_base_vseq.sv:666) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] timeout wait for alert handshake:fatal_alert
        UVM_INFO @ 10410151602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:

  • Test csrng_err has 1 failures.

    • 40.csrng_err.69930078181209375693178905803021291090410384556527302921349794351429699994107
      Line 134, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/40.csrng_err/latest/run.log

        UVM_ERROR @   2915680 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
        UVM_INFO @   2915680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test csrng_alert has 1 failures.

    • 210.csrng_alert.52126782269862452891185418084805375300887751138413963237802536393870295160537
      Line 128, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/210.csrng_alert/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---