HMAC Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.540s	1.199ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.500s	42.427us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.460s	34.063us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.430s	1.584ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	10.360s	461.971us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	24.758m	262.758ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.460s	34.063us	20	20	100.00
		hmac_csr_aliasing	10.360s	461.971us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.471m	68.540ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.641m	7.727ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.161m	5.127ms	30	30	100.00
		hmac_test_sha384_vectors	6.670m	53.094ms	75	75	100.00
		hmac_test_sha512_vectors	6.337m	23.481ms	75	75	100.00
		hmac_test_hmac256_vectors	14.450s	2.458ms	50	50	100.00
		hmac_test_hmac384_vectors	14.480s	1.270ms	60	60	100.00
		hmac_test_hmac512_vectors	15.320s	292.447us	75	75	100.00
V2	burst_wr	hmac_burst_wr	44.740s	2.332ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.113m	29.222ms	50	50	100.00
V2	error	hmac_error	1.951m	3.001ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.332m	44.453ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.540s	1.199ms	50	50	100.00
		hmac_long_msg	1.471m	68.540ms	50	50	100.00
		hmac_back_pressure	1.641m	7.727ms	50	50	100.00
		hmac_datapath_stress	21.113m	29.222ms	50	50	100.00
		hmac_burst_wr	44.740s	2.332ms	50	50	100.00
		hmac_stress_all	28.076m	15.322ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.540s	1.199ms	50	50	100.00
		hmac_long_msg	1.471m	68.540ms	50	50	100.00
		hmac_back_pressure	1.641m	7.727ms	50	50	100.00
		hmac_datapath_stress	21.113m	29.222ms	50	50	100.00
		hmac_wipe_secret	2.332m	44.453ms	50	50	100.00
		hmac_test_sha256_vectors	3.161m	5.127ms	30	30	100.00
		hmac_test_sha384_vectors	6.670m	53.094ms	75	75	100.00
		hmac_test_sha512_vectors	6.337m	23.481ms	75	75	100.00
		hmac_test_hmac256_vectors	14.450s	2.458ms	50	50	100.00
		hmac_test_hmac384_vectors	14.480s	1.270ms	60	60	100.00
		hmac_test_hmac512_vectors	15.320s	292.447us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.540s	1.199ms	50	50	100.00
		hmac_long_msg	1.471m	68.540ms	50	50	100.00
		hmac_back_pressure	1.641m	7.727ms	50	50	100.00
		hmac_datapath_stress	21.113m	29.222ms	50	50	100.00
		hmac_burst_wr	44.740s	2.332ms	50	50	100.00
		hmac_error	1.951m	3.001ms	50	50	100.00
		hmac_wipe_secret	2.332m	44.453ms	50	50	100.00
		hmac_test_sha256_vectors	3.161m	5.127ms	30	30	100.00
		hmac_test_sha384_vectors	6.670m	53.094ms	75	75	100.00
		hmac_test_sha512_vectors	6.337m	23.481ms	75	75	100.00
		hmac_test_hmac256_vectors	14.450s	2.458ms	50	50	100.00
		hmac_test_hmac384_vectors	14.480s	1.270ms	60	60	100.00
		hmac_test_hmac512_vectors	15.320s	292.447us	75	75	100.00
		hmac_stress_all	28.076m	15.322ms	50	50	100.00
V2	stress_all	hmac_stress_all	28.076m	15.322ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.070s	28.953us	50	50	100.00
V2	intr_test	hmac_intr_test	2.180s	13.615us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.390s	206.041us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.390s	206.041us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.500s	42.427us	5	5	100.00
		hmac_csr_rw	2.460s	34.063us	20	20	100.00
		hmac_csr_aliasing	10.360s	461.971us	5	5	100.00
		hmac_same_csr_outstanding	3.770s	429.788us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.500s	42.427us	5	5	100.00
		hmac_csr_rw	2.460s	34.063us	20	20	100.00
		hmac_csr_aliasing	10.360s	461.971us	5	5	100.00
		hmac_same_csr_outstanding	3.770s	429.788us	20	20	100.00
V2		TOTAL			855	855	100.00
V2S	tl_intg_err	hmac_sec_cm	2.360s	229.008us	5	5	100.00
		hmac_tl_intg_err	6.190s	824.265us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.190s	824.265us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.540s	1.199ms	50	50	100.00
V3	stress_reset	hmac_stress_reset	9.000s	452.777us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	12.546m	353.776ms	25	25	100.00
V3		TOTAL			75	75	100.00
	Unmapped tests	hmac_directed	3.060s	435.633us	1	1	100.00
		TOTAL			1061	1061	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.22	96.50	96.28	100.00	100.00	98.37	100.00	47.35