I2C Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: `371772adfd`

Branch: dj-sw-nightly

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.399m	2.913ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	38.410s	7.271ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.190s	132.736us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.810s	3.141ms	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.690s	2.007ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.950s	375.303us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.360s	54.028us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.810s	3.141ms	20	20	100.00
		i2c_csr_aliasing	2.950s	375.303us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	11.350s	1.184ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	40.530m	87.107ms	15	50	30.00
V2	host_maxperf	i2c_host_perf	47.769m	49.379ms	49	50	98.00
V2	host_override	i2c_host_override	2.270s	27.429us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.185m	9.769ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.665m	22.894ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	3.020s	174.073us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.230s	547.465us	50	50	100.00
		i2c_host_fifo_reset_rx	13.870s	454.936us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.824m	12.005ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	35.500s	1.582ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.220s	509.858us	24	50	48.00
V2	target_glitch	i2c_target_glitch	7.500s	1.866ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	9.166m	72.997ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	10.020s	983.693us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	53.970s	6.017ms	50	50	100.00
		i2c_target_intr_smoke	11.370s	7.405ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.640s	293.518us	50	50	100.00
		i2c_target_fifo_reset_tx	3.520s	410.950us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.584m	65.875ms	50	50	100.00
		i2c_target_stress_rd	53.970s	6.017ms	50	50	100.00
		i2c_target_intr_stress_wr	4.418m	18.002ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.680s	3.202ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.247m	4.932ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	9.550s	1.591ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	37.260s	10.069ms	26	50	52.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.840s	1.034ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.380s	677.661us	48	50	96.00
V2	host_mode_config_perf	i2c_host_perf	47.769m	49.379ms	49	50	98.00
		i2c_host_perf_precise	6.707m	23.152ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	35.500s	1.582ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	24.570s	1.843ms	41	50	82.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.140s	560.665us	50	50	100.00
		i2c_target_nack_acqfull_addr	5.320s	568.989us	50	50	100.00
		i2c_target_nack_txstretch	3.290s	235.703us	31	50	62.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	21.980s	2.080ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	5.030s	590.427us	50	50	100.00
V2	alert_test	i2c_alert_test	2.210s	17.453us	50	50	100.00
V2	intr_test	i2c_intr_test	2.320s	22.757us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.580s	102.260us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.580s	102.260us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.190s	132.736us	5	5	100.00
		i2c_csr_rw	2.810s	3.141ms	20	20	100.00
		i2c_csr_aliasing	2.950s	375.303us	5	5	100.00
		i2c_same_csr_outstanding	2.580s	27.325us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.190s	132.736us	5	5	100.00
		i2c_csr_rw	2.810s	3.141ms	20	20	100.00
		i2c_csr_aliasing	2.950s	375.303us	5	5	100.00
		i2c_same_csr_outstanding	2.580s	27.325us	20	20	100.00
V2		TOTAL			1671	1792	93.25
V2S	tl_intg_err	i2c_tl_intg_err	3.410s	124.392us	20	20	100.00
		i2c_sec_cm	2.590s	335.166us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.410s	124.392us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	43.100s	914.575us	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.870s	639.686us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	22.370s	3.621ms	1	10	10.00
V3		TOTAL			1	70	1.43
		TOTAL			1852	2042	90.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.20	97.35	89.89	74.17	72.62	94.32	98.51	90.53

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 46 failures:

Test i2c_host_mode_toggle has 16 failures.

0.i2c_host_mode_toggle.109130676363686390729515380983824949434239905347457385535043672634487929541662
Line 80, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 136259565 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13001

8.i2c_host_mode_toggle.62660789628822539869483600804825283669101907819041451552143093184987915027902
Line 80, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 276174866 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7251

... and 14 more failures.

Test i2c_host_stress_all has 30 failures.

4.i2c_host_stress_all.56256106995148704649698501978758604091132942435049281099137695047497845119187
Line 216, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 101994586417 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @8783296

6.i2c_host_stress_all.41101089439857764417701579090367801959914144614085225377119683152336665091762
Line 214, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 13428801445 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2293796

... and 28 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 26 failures:
- Test i2c_target_unexp_stop has 26 failures.
  - 0.i2c_target_unexp_stop.65901238321300856182213295006756182433812180180138567578141784984988376635694
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  57263621 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 120 [0x78])
  UVM_INFO @  57263621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.61704444115368972620278967648967042584937086966364612757125750337759975876390
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 163957513 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 81 [0x51])
  UVM_INFO @ 163957513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
- Test i2c_target_hrst has 24 failures.
  - 0.i2c_target_hrst.69734960641917850620265150327229635122559638632390084404604710015486737951890
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10104233741 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10104233741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.i2c_target_hrst.34415608879071391235982884051587186580835211880959170309450944937887938895689
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/9.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10051913369 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10051913369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
- Test i2c_target_unexp_stop has 20 failures.
  - 4.i2c_target_unexp_stop.35982416908335127458597415760160430741982844357017775316138745303983830930614
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  51445005 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  51445005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_unexp_stop.74036634119359365086894458836628875946583746456078438640059201764164183843126
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 426599694 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 426599694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
- Test i2c_target_nack_txstretch has 19 failures.
  - 2.i2c_target_nack_txstretch.82600287261858365170681824099721392309947269186905164515895970960863486317078
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 428954634 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 428954634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_nack_txstretch.6968521344309104280654956598859629744626466299462403787625677719257703127330
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 494970431 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 494970431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:890) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.46438220177424944022461283680005652720632993113251709142960776836254652531594
Line 79, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 209446236 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 209446236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.69722570232247500390338566357976459618072941253739093035097872902419809002585
Line 80, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5350556223 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5350556223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

0.i2c_target_stress_all_with_rand_reset.9367221628332960761024531379594309151032369294549010282991398013915662477926
Line 102, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3621465964 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3621465964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.87905883827642379629602735493434149552781295409576647188915408475357127824364
Line 91, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 837801728 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 837801728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 11 failures:
- Test i2c_target_tx_stretch_ctrl has 9 failures.
  - 6.i2c_target_tx_stretch_ctrl.96390879234866729897341097851781680280121336934974616434504884861122140504294
    Line 125, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 9.i2c_target_tx_stretch_ctrl.52604863725564227352701074710070236136092942291323684690757958664995061668499
    Line 119, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 7 more failures.
- Test i2c_target_fifo_watermarks_tx has 2 failures.
  - 16.i2c_target_fifo_watermarks_tx.62156599502881781788706219507327829787986546273208792570670281233297335083995
    Line 116, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 46.i2c_target_fifo_watermarks_tx.26713330672789738346357565509434677835676502675984098603173288173307878608371
    Line 116, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 6 failures:

Test i2c_host_mode_toggle has 6 failures.

7.i2c_host_mode_toggle.56329624942116970002697695909244999103702529486106620727207466126078273075863
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 865803022 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

18.i2c_host_mode_toggle.71981440197450916514976298420942975712154317053161609373554370474446730328809
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/18.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  50214456 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 4 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
- Test i2c_target_stretch has 5 failures.
  - 16.i2c_target_stretch.42629077742008322159805064017007462571952170133079253646016558538834185720010
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/16.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10026175070 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10026175070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.i2c_target_stretch.107008054056435549709263307805177027306882393860615291212029589611156788732139
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/26.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002233350 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002233350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:

Test i2c_target_unexp_stop has 4 failures.

24.i2c_target_unexp_stop.20959849735505689517756230541663818834962342767173385809561997546323421875732
Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/24.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1736068227 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1736068227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.i2c_target_unexp_stop.55641784853595030865381396051579482548727453429801231794019749345081323965907
Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/38.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1132495116 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1132495116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:

Test i2c_host_stress_all has 3 failures.

1.i2c_host_stress_all.102364705795019326513192010147668740146334406851127371684535592051389532165634
Line 158, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 9804080436 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @8074652

19.i2c_host_stress_all.13460650848656425650435745085381376955959014363955697344387010441736302053202
Line 345, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 132605204047 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23783078

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 10.i2c_host_mode_toggle.115628508231440190538942366332158698912677109845252373277222986090372532806353
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  31285832 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x89af8b94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  31285832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.i2c_host_mode_toggle.25365724966290973682896034239945840735667920816641552966274218325640560369115
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  36164238 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xf2167a94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  36164238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 37.i2c_host_stress_all.49569898241437550774446991846057870913878883171367750816259925827137981972888
    Log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/37.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 43.i2c_host_stress_all.95611648186475462505021330822945829925772199883814038564710350417933278527981
    Log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (cip_base_vseq.sv:794) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.102261638758628500082804210604674999753746452646223783182257007943361316294893
    Line 80, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 396920116 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 396920116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.108663321182409022503098341304900304753437103114766290133277536192017634296576
    Line 91, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  40908064 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @  40908064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 14.i2c_host_perf.19127637360804776504133968362697987594317385868174565518387188802581022321491
    Line 75, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/14.i2c_host_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 27.i2c_host_mode_toggle.4555093375100798932548056277145191232725699723628164202539630917810658885921
    Line 81, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```