KEYMGR Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 22.280s 1.309ms 50 50 100.00
V1 random keymgr_random 28.580s 6.364ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 2.470s 28.319us 5 5 100.00
V1 csr_rw keymgr_csr_rw 2.760s 33.261us 19 20 95.00
V1 csr_bit_bash keymgr_csr_bit_bash 10.080s 2.040ms 2 5 40.00
V1 csr_aliasing keymgr_csr_aliasing 13.350s 503.896us 3 5 60.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 3.340s 138.133us 15 20 75.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 2.760s 33.261us 19 20 95.00
keymgr_csr_aliasing 13.350s 503.896us 3 5 60.00
V1 TOTAL 144 155 92.90
V2 cfgen_during_op keymgr_cfg_regwen 1.494m 10.366ms 47 50 94.00
V2 sideload keymgr_sideload 23.200s 1.078ms 50 50 100.00
keymgr_sideload_kmac 28.320s 1.575ms 50 50 100.00
keymgr_sideload_aes 55.000s 7.467ms 49 50 98.00
keymgr_sideload_otbn 37.020s 2.368ms 48 50 96.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 7.920s 1.612ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 24.310s 1.281ms 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 8.520s 764.897us 32 50 64.00
V2 invalid_sw_input keymgr_sw_invalid_input 56.900s 7.639ms 49 50 98.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 36.440s 2.148ms 48 50 96.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 19.860s 2.971ms 40 50 80.00
V2 stress_all keymgr_stress_all 4.167m 51.951ms 45 50 90.00
V2 intr_test keymgr_intr_test 2.360s 10.254us 50 50 100.00
V2 alert_test keymgr_alert_test 2.370s 24.341us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.420s 1.020ms 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.420s 1.020ms 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 2.470s 28.319us 5 5 100.00
keymgr_csr_rw 2.760s 33.261us 19 20 95.00
keymgr_csr_aliasing 13.350s 503.896us 3 5 60.00
keymgr_same_csr_outstanding 3.480s 85.784us 16 20 80.00
V2 tl_d_partial_access keymgr_csr_hw_reset 2.470s 28.319us 5 5 100.00
keymgr_csr_rw 2.760s 33.261us 19 20 95.00
keymgr_csr_aliasing 13.350s 503.896us 3 5 60.00
keymgr_same_csr_outstanding 3.480s 85.784us 16 20 80.00
V2 TOTAL 694 740 93.78
V2S sec_cm_additional_check keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 16.340s 646.371us 5 5 100.00
keymgr_tl_intg_err 5.190s 206.019us 16 20 80.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 4.360s 164.726us 3 20 15.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 4.360s 164.726us 3 20 15.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 4.360s 164.726us 3 20 15.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 4.360s 164.726us 3 20 15.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 8.750s 1.169ms 6 20 30.00
V2S prim_count_check keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 5.190s 206.019us 16 20 80.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 4.360s 164.726us 3 20 15.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.494m 10.366ms 47 50 94.00
V2S sec_cm_reseed_config_regwen keymgr_random 28.580s 6.364ms 50 50 100.00
keymgr_csr_rw 2.760s 33.261us 19 20 95.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 28.580s 6.364ms 50 50 100.00
keymgr_csr_rw 2.760s 33.261us 19 20 95.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 28.580s 6.364ms 50 50 100.00
keymgr_csr_rw 2.760s 33.261us 19 20 95.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 24.310s 1.281ms 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 36.440s 2.148ms 48 50 96.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 36.440s 2.148ms 48 50 96.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 28.580s 6.364ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 22.840s 1.699ms 49 50 98.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 8.780s 1.484ms 37 50 74.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 24.310s 1.281ms 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 8.780s 1.484ms 37 50 74.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 8.780s 1.484ms 37 50 74.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 8.780s 1.484ms 37 50 74.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 16.340s 646.371us 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 8.780s 1.484ms 37 50 74.00
V2S TOTAL 116 165 70.30
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 22.650s 13.416ms 30 50 60.00
V3 TOTAL 30 50 60.00
TOTAL 984 1110 88.65

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.72 99.10 97.87 98.24 100.00 99.01 98.61 91.22

Failure Buckets