371772adfd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.488m | 15.099ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 2.470s | 134.136us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 2.580s | 48.964us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 25.850s | 6.027ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 8.260s | 137.001us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.850s | 332.795us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 2.580s | 48.964us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 8.260s | 137.001us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 2.180s | 18.622us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 3.020s | 64.832us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 49.585m | 266.441ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 21.189m | 145.616ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 32.433m | 62.263ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 32.696m | 116.569ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 26.793m | 234.354ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 18.372m | 125.314ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 38.595m | 115.335ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 27.315m | 60.286ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 4.590s | 1.496ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 4.310s | 82.492us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 7.201m | 31.354ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 5.145m | 48.243ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.996m | 80.097ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 5.954m | 13.848ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 7.197m | 76.560ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 18.000s | 7.969ms | 50 | 50 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 9.720s | 229.671us | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 42.750s | 3.006ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 53.410s | 8.254ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.474m | 102.451ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 29.670s | 3.167ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 37.297m | 416.371ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 2.310s | 51.002us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 2.460s | 50.424us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 5.020s | 1.451ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 5.020s | 1.451ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 2.470s | 134.136us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.580s | 48.964us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 8.260s | 137.001us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 4.160s | 487.502us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 2.470s | 134.136us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.580s | 48.964us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 8.260s | 137.001us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 4.160s | 487.502us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 740 | 740 | 100.00 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 3.080s | 45.887us | 6 | 20 | 30.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 3.080s | 45.887us | 6 | 20 | 30.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 3.080s | 45.887us | 6 | 20 | 30.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 3.080s | 45.887us | 6 | 20 | 30.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 4.680s | 207.427us | 7 | 20 | 35.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.794m | 31.386ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 6.410s | 1.071ms | 16 | 20 | 80.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 6.410s | 1.071ms | 16 | 20 | 80.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 29.670s | 3.167ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.488m | 15.099ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 7.201m | 31.354ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 3.080s | 45.887us | 6 | 20 | 30.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.794m | 31.386ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.794m | 31.386ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.794m | 31.386ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.488m | 15.099ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 29.670s | 3.167ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.794m | 31.386ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.004m | 41.381ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.488m | 15.099ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 44 | 75 | 58.67 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 2.691m | 2.454ms | 8 | 10 | 80.00 |
| V3 | TOTAL | 8 | 10 | 80.00 | |||
| TOTAL | 907 | 940 | 96.49 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.35 | 99.18 | 94.47 | 99.89 | 79.58 | 97.09 | 99.36 | 97.88 |
UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 21 failures:
0.kmac_shadow_reg_errors.92006352172986723920636759273495772304569420110595710421926069328618776290921
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log
UVM_FATAL @ 155749729 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 155749729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_shadow_reg_errors.96315328926655562683800224802912824002356661479303955280431939628024277216217
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log
UVM_FATAL @ 52238942 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 52238942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.kmac_shadow_reg_errors_with_csr_rw.53183108572303251185577162954925042468232124410958456605426881429845784054307
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 59150034 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 59150034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_shadow_reg_errors_with_csr_rw.16151142698967191220341670312296072672901426700005248793585359554381850044012
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 13620089 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 13620089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 8 failures:
2.kmac_tl_intg_err.91141898459011401365503082214450536317091691263462295950168664965877021600061
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
UVM_ERROR @ 9360403 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
UVM_INFO @ 9360403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.kmac_tl_intg_err.77252562573474988509260582434199290896135223696915261105157698852377450099224
Line 79, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
UVM_ERROR @ 38081308 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
UVM_INFO @ 38081308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
4.kmac_shadow_reg_errors_with_csr_rw.43323894658924831397885007329231101145344478358712788671107506397102873694871
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
UVM_ERROR @ 14851132 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
UVM_INFO @ 14851132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.kmac_shadow_reg_errors_with_csr_rw.59712246487779498180058565069453394495806250747774110763946509556982233276345
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
UVM_ERROR @ 25718555 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
UVM_INFO @ 25718555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:969) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 2 failures:
1.kmac_shadow_reg_errors_with_csr_rw.22056351395265665705927682215011369501076122998670558959931797908464262941154
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 70201166 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
UVM_INFO @ 70201166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_shadow_reg_errors_with_csr_rw.71019337485980075299213672484439898666140174047637576542387676791597305127035
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 67682406 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
UVM_INFO @ 67682406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
2.kmac_stress_all_with_rand_reset.37008619089245792193008971181236587625803103629803547732559045378360752886129
Line 141, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4842801932 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
UVM_INFO @ 4842801932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.94380171328350358594647156772779947163362795375451673847456713733132688064122
Line 80, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 241447049 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
UVM_INFO @ 241447049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---