371772adfd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 57.700s | 33.543ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 2.580s | 82.066us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 2.470s | 14.413us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 18.950s | 19.273ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.710s | 1.513ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.840s | 360.468us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 2.470s | 14.413us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.710s | 1.513ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 2.230s | 12.728us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 2.880s | 456.424us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 44.933m | 293.294ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 14.351m | 144.173ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 24.655m | 339.484ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 45.780s | 4.764ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 18.834m | 244.829ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 13.284m | 126.109ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 22.221m | 20.741ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 26.886m | 59.132ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 3.590s | 420.666us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.710s | 306.698us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 6.325m | 58.060ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 4.206m | 51.581ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 3.439m | 36.990ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 4.261m | 14.212ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 5.605m | 70.226ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 17.730s | 10.869ms | 49 | 50 | 98.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.147m | 10.080ms | 42 | 50 | 84.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 40.650s | 4.352ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 35.900s | 33.763ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 55.490s | 65.964ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 31.180s | 583.851us | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 27.803m | 95.324ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 2.390s | 54.763us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 2.300s | 73.348us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.260s | 670.808us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.260s | 670.808us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 2.580s | 82.066us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.470s | 14.413us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.710s | 1.513ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.910s | 368.716us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 2.580s | 82.066us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.470s | 14.413us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.710s | 1.513ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.910s | 368.716us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 730 | 740 | 98.65 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 3.210s | 61.391us | 8 | 20 | 40.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 3.210s | 61.391us | 8 | 20 | 40.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 3.210s | 61.391us | 8 | 20 | 40.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 3.210s | 61.391us | 8 | 20 | 40.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 4.750s | 155.732us | 7 | 20 | 35.00 |
| V2S | tl_intg_err | kmac_sec_cm | 58.160s | 19.887ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.460s | 349.391us | 15 | 20 | 75.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.460s | 349.391us | 15 | 20 | 75.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 31.180s | 583.851us | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 57.700s | 33.543ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 6.325m | 58.060ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 3.210s | 61.391us | 8 | 20 | 40.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 58.160s | 19.887ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 58.160s | 19.887ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 58.160s | 19.887ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 57.700s | 33.543ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 31.180s | 583.851us | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 58.160s | 19.887ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 4.280m | 50.589ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 57.700s | 33.543ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 45 | 75 | 60.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 2.434m | 14.586ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 894 | 940 | 95.11 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.62 | 97.60 | 94.38 | 100.00 | 71.90 | 95.98 | 99.34 | 96.15 |
UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 20 failures:
3.kmac_shadow_reg_errors.107202310037061549281001163269098722122404800150526312415207149996708532631535
Line 85, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log
UVM_FATAL @ 15757105 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 15757105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_shadow_reg_errors.11387448881230817697304803462231452569578932043177116186750685315435717301758
Line 85, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log
UVM_FATAL @ 43319363 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 43319363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
3.kmac_shadow_reg_errors_with_csr_rw.64943174802206120468999019456103972681416117725322064337995226780838722286674
Line 86, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 374739133 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 374739133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.kmac_shadow_reg_errors_with_csr_rw.98435413419205596810236784418128799654762249992053981966538457180591240508515
Line 85, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 7181336 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 7181336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 9 failures:
0.kmac_shadow_reg_errors_with_csr_rw.10791626068428209345287680509269175271715765942398934208520343310160249114289
Line 86, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
UVM_ERROR @ 22232997 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
UVM_INFO @ 22232997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_shadow_reg_errors_with_csr_rw.81589639067295297804639016339862122260553964952377288841955490675822274759694
Line 86, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
UVM_ERROR @ 15007060 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
UVM_INFO @ 15007060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
0.kmac_tl_intg_err.114341512791426911359182803607259803855257640523899610744997209537929795583618
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
UVM_ERROR @ 112754336 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
UVM_INFO @ 112754336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.kmac_tl_intg_err.30105362781061181723442903587321179596536031821183985277268537148494252193967
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
UVM_ERROR @ 27457671 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
UVM_INFO @ 27457671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
4.kmac_stress_all_with_rand_reset.43260748674952111434214560815024117024791179669020637094975065905992138603075
Line 197, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11081402070 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
UVM_INFO @ 11081402070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.83368025510283485066722483751405174998483864505351749780812086517069542906034
Line 169, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8497812916 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
UVM_INFO @ 8497812916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:890) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
2.kmac_stress_all_with_rand_reset.14602145998149800578052338625009571196457295003810936064502291181375656642179
Line 128, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14363416201 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14363416201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.kmac_stress_all_with_rand_reset.69577782325342894390541842598097556886498370382999399898876686184049966057277
Line 127, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13558228964 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13558228964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
2.kmac_sideload_invalid.75039497012687085403655721893899540165754711606140788447726738394154235011170
Line 83, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10113077686 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xde65000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10113077686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
5.kmac_sideload_invalid.65576474598456966056220278178286917598250738634007451738993589908163458233998
Line 79, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10235593184 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaf9a5000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10235593184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:969) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:
7.kmac_shadow_reg_errors.17972534335367733770728825096136757127591321570115566713428801398144911403011
Line 86, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest/run.log
UVM_ERROR @ 64710529 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
UVM_INFO @ 64710529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
16.kmac_sideload_invalid.62486457225987046424503617695003175181704151334283834993965122197700632768473
Line 94, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10080204591 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe753000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10080204591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
18.kmac_sideload_invalid.59722756501170566639729853935450844625653671130297336129224465826916596550508
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10018364110 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfe74c000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10018364110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
27.kmac_sideload_invalid.109483452093962023568532737169137476140433256287107299094112675737676189852234
Line 79, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10055321877 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x995e6000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10055321877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
31.kmac_sideload_invalid.65688617030810864261651741546880848011143405934992852627906820593365645763655
Line 77, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10077618897 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfcab0000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10077618897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
32.kmac_sideload_invalid.19463836462646597607498840095452438463940124085458066365148952710479244352962
Line 73, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10016418622 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xef950000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10016418622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
35.kmac_sideload_invalid.24627347264957424088837021762014531411809322097951444561585241743937188489353
Line 88, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10282922077 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x864e8000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10282922077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
36.kmac_error.95758309985187043948077322599497026134732107659457311695282370117955809672230
Line 179, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/36.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
41.kmac_key_error.58251387086941732511410865450757612775538921494565384862363969973537392302069
Line 72, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/41.kmac_key_error/latest/run.log
UVM_ERROR @ 46959379 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
UVM_INFO @ 46959379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---