OTBN Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: `371772adfd`

Branch: dj-sw-nightly

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	37.236us	1	1	100.00
V1	single_binary	otbn_single	25.000s	563.197us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	21.486us	5	5	100.00
V1	csr_rw	otbn_csr_rw	11.000s	93.782us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	33.923us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	14.082us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	30.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	11.000s	93.782us	20	20	100.00
		otbn_csr_aliasing	7.000s	14.082us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	1.259ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	462.719us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	30.000s	561.579us	10	10	100.00
V2	multi_error	otbn_multi_err	1.250m	213.911us	1	1	100.00
V2	back_to_back	otbn_multi	2.217m	5.243ms	9	10	90.00
V2	stress_all	otbn_stress_all	1.267m	418.793us	10	10	100.00
V2	lc_escalation	otbn_escalate	59.000s	296.144us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	45.364us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	154.035us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	24.038us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	22.654us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	107.848us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	107.848us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	21.486us	5	5	100.00
		otbn_csr_rw	11.000s	93.782us	20	20	100.00
		otbn_csr_aliasing	7.000s	14.082us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	34.758us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	21.486us	5	5	100.00
		otbn_csr_rw	11.000s	93.782us	20	20	100.00
		otbn_csr_aliasing	7.000s	14.082us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	34.758us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	15.000s	43.849us	10	10	100.00
		otbn_dmem_err	23.000s	333.843us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	71.915us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	65.036us	5	5	100.00
		otbn_mac_bignum_acc_err	46.000s	190.665us	4	5	80.00
		otbn_urnd_err	8.000s	26.020us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	14.000s	47.100us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	1.033m	927.863us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	28.071us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
		otbn_tl_intg_err	42.000s	1.078ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	228.223us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	37.236us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	23.000s	333.843us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	43.849us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	42.000s	1.078ms	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	59.000s	296.144us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	43.849us	10	10	100.00
		otbn_dmem_err	23.000s	333.843us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	45.364us	5	5	100.00
		otbn_illegal_mem_acc	14.000s	47.100us	5	5	100.00
		otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	43.849us	10	10	100.00
		otbn_dmem_err	23.000s	333.843us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	45.364us	5	5	100.00
		otbn_illegal_mem_acc	14.000s	47.100us	5	5	100.00
		otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	59.000s	296.144us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	43.849us	10	10	100.00
		otbn_dmem_err	23.000s	333.843us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	45.364us	5	5	100.00
		otbn_illegal_mem_acc	14.000s	47.100us	5	5	100.00
		otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	28.471us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	56.921us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	56.000s	368.621us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	56.000s	368.621us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	63.637us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	68.405us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.200m	293.537us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.200m	293.537us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	20.512s		4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.217m	5.243ms	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	21.000s	124.196us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	25.000s	563.197us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.433m	5.626ms	4	5	80.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.533m	1.984ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			571	585	97.61

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.01	99.55	94.63	99.67	93.32	93.44	100.00	97.70	99.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 0.otbn_stress_all_with_rand_reset.48899197731394446695242039902251613739139129625080970526411033790943568304898
    Line 169, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 464873612 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 464873612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_stress_all_with_rand_reset.109879144638495369820419473633646128124877607804304895074384462302708404392511
    Line 180, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 995996782 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 995996782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal has unexpected timeout error has 2 failures:
- Test otbn_mac_bignum_acc_err has 1 failures.
  - 1.otbn_mac_bignum_acc_err.46852120557497191184338074234441601876655590101405140868534287044116024164707
    Line 121, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/1.otbn_mac_bignum_acc_err/latest/run.log
```
  UVM_ERROR @  89453621 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal has unexpected timeout error
  UVM_INFO @  89453621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.25786370760025283540308325379458279144674762946325886770185636717998468402076
    Line 473, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2024075303 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal has unexpected timeout error
  UVM_INFO @ 2024075303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_sec_wipe_err has 2 failures.

1.otbn_sec_wipe_err.16616262687127127297029938780163124489174337721445097178115500506919687161317
Line 110, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35590707 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35590707 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  35590707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_sec_wipe_err.96117115101445068829289620700513794761559477236429929517088312051743559509030
Line 136, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 31425888 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  31425888 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  31425888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 1 failures:

Test otbn_sec_wipe_err has 1 failures.

0.otbn_sec_wipe_err.24285130572641624789614055899625467921539032453840625523442461178282451241194
Log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 24285130572641624789614055899625467921539032453840625523442461178282451241194 --size 2000 --count 1 /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest run_opts='+otbn_elf_dir=/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=3156838634 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_sec_wipe_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/coverage/default/0.otbn_sec_wipe_err.3156838634 -covworkdir /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_sec_wipe_err.3156838634 -covoverwrite' seed=24285130572641624789614055899625467921539032453840625523442461178282451241194 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_sec_wipe_err_vseq

  [make]: pre_run
  mkdir -p /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest
  cd /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 24285130572641624789614055899625467921539032453840625523442461178282451241194 --size 2000 --count 1 /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/otbn-binaries
  ~/opentitan ~/scratch/dj-sw-nightly/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest
  2025/03/08 07:59:26 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
  Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
  FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36

xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

2.otbn_sec_cm.15556942949346690507030456102318143393269720300163533613841981395988670585106
Line 102, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 19249923 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 19249923 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 19249923 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 19249923 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 19249923 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.34320698152088988474727651774244473707427636876686337198050514516565388604624
    Line 408, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1984037486 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1984037486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
- Test otbn_multi has 1 failures.
  - 9.otbn_multi.68565405823558025866814743964993968434576572509634461112886069973529465063762
    Line 190, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/9.otbn_multi/latest/run.log
```
  UVM_FATAL @ 407221218 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 407221218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 40.otbn_escalate.75389257439806233325668701291804307964734440649960306330686495404187153595113
    Line 102, in log /nightly/runs/scratch/dj-sw-nightly/otbn-sim-xcelium/40.otbn_escalate/latest/run.log
```
  UVM_ERROR @   6955988 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   6955988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```