RV_DM/USE_DMI_INTERFACE Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.930s	1.048us	0	2	0.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.160s	1.511us	0	5	0.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.270s	1.627us	0	20	0.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	2.220s	658.445ns	0	5	0.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.250s	984.144ns	0	5	0.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	2.230s	920.056ns	0	5	0.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	2.270s	613.414ns	0	20	0.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.190s	595.702ns	0	20	0.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.070s	1.311us	0	5	0.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.730s	598.879ns	0	2	0.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.030s	923.143ns	0	2	0.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.930s	3.821us	0	2	0.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.210s	3.896us	0	2	0.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.840s	647.270ns	0	2	0.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.980s	1.070us	0	2	0.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.720s	869.118ns	0	2	0.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.080s	748.240ns	0	8	0.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.730s	598.879ns	0	2	0.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.830s	1.780us	0	2	0.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.790s	568.231ns	0	2	0.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.930s	3.821us	0	2	0.00
V1	rom_read_access	rv_dm_rom_read_access	2.070s	4.131us	0	2	0.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.210s	1.193us	0	5	0.00
V1	csr_rw	rv_dm_csr_rw	2.240s	1.993us	0	20	0.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	2.240s	589.506ns	0	5	0.00
V1	csr_aliasing	rv_dm_csr_aliasing	2.260s	1.005us	0	5	0.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	2.310s	4.152us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	2.260s	1.005us	0	5	0.00
		rv_dm_csr_rw	2.240s	1.993us	0	20	0.00
V1	mem_walk	rv_dm_mem_walk	2.270s	3.755us	0	5	0.00
V1	mem_partial_access	rv_dm_mem_partial_access	2.260s	799.484ns	0	5	0.00
V1		TOTAL			0	180	0.00
V2	idcode	rv_dm_smoke	1.930s	1.048us	0	2	0.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.800s	700.050ns	0	2	0.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.810s	2.402us	0	2	0.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.890s	595.903ns	0	2	0.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.760s	1.997us	0	2	0.00
V2	sba	rv_dm_sba_tl_access	2.390s	2.128us	0	20	0.00
		rv_dm_delayed_resp_sba_tl_access	2.430s	820.036ns	0	20	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	2.400s	1.271us	0	20	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.440s	753.238ns	0	20	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.830s	714.687ns	0	2	0.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	1.900s	768.777ns	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.830s	2.471us	0	2	0.00
V2	hart_unavail	rv_dm_hart_unavail	1.850s	648.933ns	0	5	0.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	1.780s	1.081us	0	1	0.00
		rv_dm_tap_fsm_rand_reset	2.190s	708.162ns	0	10	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.800s	2.847us	0	1	0.00
V2	stress_all	rv_dm_stress_all	2.420s	785.662ns	0	50	0.00
V2	alert_test	rv_dm_alert_test	2.450s	958.900ns	0	50	0.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	2.250s	2.639us	0	20	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	2.250s	2.639us	0	20	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	2.260s	1.005us	0	5	0.00
		rv_dm_csr_hw_reset	2.210s	1.193us	0	5	0.00
		rv_dm_csr_rw	2.240s	1.993us	0	20	0.00
		rv_dm_same_csr_outstanding	2.150s	680.087ns	0	20	0.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	2.260s	1.005us	0	5	0.00
		rv_dm_csr_hw_reset	2.210s	1.193us	0	5	0.00
		rv_dm_csr_rw	2.240s	1.993us	0	20	0.00
		rv_dm_same_csr_outstanding	2.150s	680.087ns	0	20	0.00
V2		TOTAL			0	251	0.00
V2S	tl_intg_err	rv_dm_sec_cm	1.970s	5.663us	0	5	0.00
		rv_dm_tl_intg_err	2.270s	6.942us	0	20	0.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	2.270s	6.942us	0	20	0.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	1.900s	768.777ns	0	2	0.00
		rv_dm_debug_disabled	2.020s	747.775ns	0	2	0.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	1.900s	768.777ns	0	2	0.00
		rv_dm_debug_disabled	2.020s	747.775ns	0	2	0.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.930s	1.048us	0	2	0.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.310s	2.351us	0	10	0.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	2.050s	1.789us	0	4	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	2.050s	1.789us	0	4	0.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.310s	2.351us	0	10	0.00
V2S		TOTAL			0	41	0.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.480s	757.794ns	0	10	0.00
V3		TOTAL			0	10	0.00
	Unmapped tests	rv_dm_scanmode	1.740s	1.354us	0	1	0.00
		TOTAL			0	483	0.00

Failure Buckets

• Offending '(!$isunknown(lc_en_o))' has 483 failures:

  • Test rv_dm_csr_aliasing has 5 failures.

    • 0.rv_dm_csr_aliasing.94444796319866480066375544954712376465173599911237659643845290999522125882704
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   1004558 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   1004558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_csr_aliasing.31343631652052076315867131392745859591868886101933587092545946758587356841859
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2580414 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2580414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test rv_dm_smoke has 2 failures.

    • 0.rv_dm_smoke.83769591901460698944202344403937583185448957083881981973448414449751941682123
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   1047617 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   1047617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_smoke.109007451556714055400853044896757400745962749972669062144239976876366962034212
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_smoke/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @    770437 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @    770437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_tap_fsm has 1 failures.

    • 0.rv_dm_tap_fsm.30898541963179475660303353585596335549013173302829729743001948138682899856524
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   1081028 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   1081028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.

    • 0.rv_dm_jtag_dtm_csr_hw_reset.36999383000626309887094113882561962575323851340791414173716264732124433111729
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @    949815 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @    949815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_jtag_dtm_csr_hw_reset.100304139496569486802157781888892626302827140830062540788448459857559467163348
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   1510669 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   1510669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test rv_dm_jtag_dtm_csr_rw has 20 failures.

    • 0.rv_dm_jtag_dtm_csr_rw.39183021721041562351854863354113131072524942107356006770127345683367622231293
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   1003696 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   1003696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_jtag_dtm_csr_rw.28977745742440084323452900918326648122077907456208792865747828604637756650907
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   1627301 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   1627301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 18 more failures.

  • ... and 48 more tests.

• Job killed most likely because its dependent job failed. has 2 failures:
  • Test rv_dm has 2 failures.

    • cov_merge
      Log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/cov_merge/merged.vdb/cov_merge.log

    • cov_report
      Log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/cov_report/cov_report.log