RV_TIMER Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	31.569m	272.348ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.150s	122.447us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.260s	35.374us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.290s	280.675us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.340s	19.781us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.950s	31.547us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.260s	35.374us	20	20	100.00
		rv_timer_csr_aliasing	2.340s	19.781us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	25.809m	94.422ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.450m	590.347ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	17.838m	4.545s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	17.838m	4.545s	50	50	100.00
V2	stress	rv_timer_stress_all	39.193m	697.594ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.280s	11.919us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.140s	525.221us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.140s	525.221us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.150s	122.447us	5	5	100.00
		rv_timer_csr_rw	2.260s	35.374us	20	20	100.00
		rv_timer_csr_aliasing	2.340s	19.781us	5	5	100.00
		rv_timer_same_csr_outstanding	2.370s	32.338us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.150s	122.447us	5	5	100.00
		rv_timer_csr_rw	2.260s	35.374us	20	20	100.00
		rv_timer_csr_aliasing	2.340s	19.781us	5	5	100.00
		rv_timer_same_csr_outstanding	2.370s	32.338us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	1.940s	87.372us	5	5	100.00
		rv_timer_tl_intg_err	2.970s	365.358us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.970s	365.358us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.170m	5.915ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			581	620	93.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.82	100.00	99.36	100.00	--	100.00	100.00	99.55

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:890) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
  • Test rv_timer_stress_all_with_rand_reset has 38 failures.

    • 0.rv_timer_stress_all_with_rand_reset.112210522226690241262943747924203403137264675104972029918896573610516833969791
      Line 91, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3378996816 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10045 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3378996816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.rv_timer_stress_all_with_rand_reset.62689340096257925050949723855014040790115111068576960827361808185480671268053
      Line 114, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1101839048 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1101839048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 36 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test rv_timer_disabled has 1 failures.

    • 41.rv_timer_disabled.115352049266875724953185029972805811344611042566215302966218593690510987774516
      Line 71, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/41.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---