SPI_HOST Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	3.517m	6.716ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	54.316us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	45.752us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	159.923us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	28.453us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	46.895us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	45.752us	20	20	100.00
		spi_host_csr_aliasing	5.000s	28.453us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	143.641us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	29.019us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	44.000s	115.872us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.517m	14.868ms	50	50	100.00
		spi_host_error_cmd	44.000s	40.176us	50	50	100.00
		spi_host_event	3.383m	79.451ms	50	50	100.00
V2	clock_rate	spi_host_speed	46.000s	75.025us	49	50	98.00
V2	speed	spi_host_speed	46.000s	75.025us	49	50	98.00
V2	chip_select_timing	spi_host_speed	46.000s	75.025us	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.133m	13.162ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	44.000s	808.052us	50	50	100.00
V2	cpol_cpha	spi_host_speed	46.000s	75.025us	49	50	98.00
V2	full_cycle	spi_host_speed	46.000s	75.025us	49	50	98.00
V2	duplex	spi_host_smoke	3.517m	6.716ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	3.517m	6.716ms	50	50	100.00
V2	stress_all	spi_host_stress_all	4.567m	15.025ms	49	50	98.00
V2	spien	spi_host_spien	3.433m	6.195ms	50	50	100.00
V2	stall	spi_host_status_stall	4.333m	28.827ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	42.000s	187.849us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.517m	14.868ms	50	50	100.00
V2	alert_test	spi_host_alert_test	42.000s	16.351us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	41.693us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	365.491us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	365.491us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	54.316us	5	5	100.00
		spi_host_csr_rw	5.000s	45.752us	20	20	100.00
		spi_host_csr_aliasing	5.000s	28.453us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	23.680us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	54.316us	5	5	100.00
		spi_host_csr_rw	5.000s	45.752us	20	20	100.00
		spi_host_csr_aliasing	5.000s	28.453us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	23.680us	20	20	100.00
V2		TOTAL			685	690	99.28
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	115.592us	20	20	100.00
		spi_host_sec_cm	42.000s	202.549us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	115.592us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	54.217m	200.000ms	2	10	20.00
		TOTAL			827	840	98.45

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.29	96.76	93.24	98.70	94.61	88.02	100.00	97.21	91.29

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test spi_host_upper_range_clkdiv has 3 failures.

    • 2.spi_host_upper_range_clkdiv.30605578072906300639343558068901432347455899972921039997186266461451271460969
      Line 229, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.spi_host_upper_range_clkdiv.537661173223557825535745026528356455379350213124345353712734190911495016082
      Line 207, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:

  • Test spi_host_upper_range_clkdiv has 3 failures.

    • 4.spi_host_upper_range_clkdiv.79473047175932901366539385167901817516465153533624886271077358560404963994458
      Line 225, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100000711116 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xf18e6b14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100000711116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.spi_host_upper_range_clkdiv.88317234069842070983964452053595090023858541088300237798789894109488866585085
      Line 164, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100004268108 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x30926dd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100004268108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Job timed out after * minutes has 2 failures:

  • Test spi_host_upper_range_clkdiv has 2 failures.

    • 3.spi_host_upper_range_clkdiv.68738362972917815128845016204599851769659099483110233727799589051334183272280
      Log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

    • 9.spi_host_upper_range_clkdiv.49102789518246506304799119821890617981636761608701905044145079393432485327264
      Log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=75) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 10.spi_host_status_stall.98284967725507998894812983224196949552487867946496614597059603784360232463758
      Line 661, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/10.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 13262654059 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb6a09914, Comparison=CompareOpEq, exp_data=0x1, call_count=75)
        UVM_INFO @ 13262654059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=117) has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 15.spi_host_speed.103083068918928871141837148990210568570641581839583242663108931436721676869634
      Line 665, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/15.spi_host_speed/latest/run.log

        UVM_FATAL @ 10099061621 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x6d811b14, Comparison=CompareOpEq, exp_data=0x0, call_count=117)
        UVM_INFO @ 10099061621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 20.spi_host_status_stall.101902834320792948670966571286803617009214804168846843161559011226048238698374
      Line 697, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 11135168353 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xdd476ed4, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
        UVM_INFO @ 11135168353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:

  • Test spi_host_stress_all has 1 failures.

    • 30.spi_host_stress_all.90040531429762098940394491722333886609568198488061021627718523086495313528385
      Line 188, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/30.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 15024573991 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x54d84214, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
        UVM_INFO @ 15024573991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=91) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 32.spi_host_status_stall.75210208894227767988587604588637746130307288015802846671551910109966002619504
      Line 756, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/32.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 11368866269 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xb54dc7d4, Comparison=CompareOpEq, exp_data=0x1, call_count=91)
        UVM_INFO @ 11368866269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---