UART Simulation Results

Friday March 07 2025 17:56:47 UTC

GitHub Revision: 371772adfd

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	29.450s	11.038ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.990s	1.033ms	5	5	100.00
V1	csr_rw	uart_csr_rw	2.350s	13.888us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.840s	229.934us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.700s	77.983us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.850s	125.119us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.350s	13.888us	20	20	100.00
		uart_csr_aliasing	2.700s	77.983us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.242m	190.610ms	50	50	100.00
V2	parity	uart_smoke	29.450s	11.038ms	50	50	100.00
		uart_tx_rx	2.242m	190.610ms	50	50	100.00
V2	parity_error	uart_intr	13.899m	661.584ms	50	50	100.00
		uart_rx_parity_err	12.247m	185.004ms	50	50	100.00
V2	watermark	uart_tx_rx	2.242m	190.610ms	50	50	100.00
		uart_intr	13.899m	661.584ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.401m	141.041ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.064m	143.786ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.832m	165.320ms	300	300	100.00
V2	rx_frame_err	uart_intr	13.899m	661.584ms	50	50	100.00
V2	rx_break_err	uart_intr	13.899m	661.584ms	50	50	100.00
V2	rx_timeout	uart_intr	13.899m	661.584ms	50	50	100.00
V2	perf	uart_perf	14.630m	18.731ms	49	50	98.00
V2	sys_loopback	uart_loopback	40.760s	15.460ms	50	50	100.00
V2	line_loopback	uart_loopback	40.760s	15.460ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.455m	119.023ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.219m	30.514ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	33.780s	11.944ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.042m	6.319ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	12.383m	142.189ms	48	50	96.00
V2	stress_all	uart_stress_all	32.206m	529.100ms	50	50	100.00
V2	alert_test	uart_alert_test	2.180s	134.590us	50	50	100.00
V2	intr_test	uart_intr_test	2.300s	15.418us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.600s	1.253ms	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.600s	1.253ms	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.990s	1.033ms	5	5	100.00
		uart_csr_rw	2.350s	13.888us	20	20	100.00
		uart_csr_aliasing	2.700s	77.983us	5	5	100.00
		uart_same_csr_outstanding	2.330s	23.801us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.990s	1.033ms	5	5	100.00
		uart_csr_rw	2.350s	13.888us	20	20	100.00
		uart_csr_aliasing	2.700s	77.983us	5	5	100.00
		uart_same_csr_outstanding	2.330s	23.801us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	2.570s	733.233us	5	5	100.00
		uart_tl_intg_err	2.700s	260.285us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.700s	260.285us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.662m	4.750ms	95	100	95.00
V3		TOTAL			95	100	95.00
		TOTAL			1312	1320	99.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.18	98.25	91.55	--	98.14	100.00	99.55

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

  • Test uart_perf has 1 failures.

    • 19.uart_perf.50352975012327700251135244255834497023307157150254360875143499008878109908873
      Line 69, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/19.uart_perf/latest/run.log

        UVM_ERROR @   1002575 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 2855605723 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/6
        UVM_INFO @ 2900043258 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/6
        UVM_INFO @ 2900418270 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/6
        UVM_INFO @ 4288768637 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/6
      

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 52.uart_stress_all_with_rand_reset.47797444715389139431826466253819291851312794894200754045841062183489778203804
      Line 145, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10167732850 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 10197808848 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 4/10
        UVM_INFO @ 10197990668 ps: (cip_base_vseq.sv:818) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 4/10
      

    • 74.uart_stress_all_with_rand_reset.26221265712800702579911846118479648199860216086187131124943602291815902490477
      Line 208, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16386080931 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 16793357731 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/575
        UVM_INFO @ 17005087121 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/575
        UVM_INFO @ 17491728351 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/575
        UVM_INFO @ 17999051606 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/575
      

• UVM_ERROR (cip_base_vseq.sv:794) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test uart_stress_all_with_rand_reset has 2 failures.

    • 3.uart_stress_all_with_rand_reset.65001002988892366834861495562043782340146026466067912472330817591725099733547
      Line 79, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 205522097 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 205522097 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 2/5
        UVM_INFO @ 205583321 ps: (cip_base_vseq.sv:818) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 2/5
      

    • 75.uart_stress_all_with_rand_reset.33972667489209039474487922765649263486841029786863719739564675452645020170553
      Line 88, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1215283013 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1215283013 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 3/10
        UVM_INFO @ 1215283013 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/5
        UVM_INFO @ 1215363013 ps: (cip_base_vseq.sv:818) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 7.uart_long_xfer_wo_dly.35600690588320516071832402562469919162091475439504741665580919154610130105574
      Line 72, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @ 77594929673 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_ERROR @ 78517054697 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_INFO @ 81851081369 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/5
        UVM_INFO @ 121028688905 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/5
        UVM_INFO @ 162712022329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
      

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 33.uart_long_xfer_wo_dly.8853250671414720201417819980890224350272935144763657611650804039999967642722
      Line 74, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @ 65506128581 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 66102015701 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 67057846877 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_INFO @ 72120416789 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/10
        UVM_ERROR @ 72736421717 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
      

• UVM_ERROR (cip_base_vseq.sv:890) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 95.uart_stress_all_with_rand_reset.111562069663259829995586843619490119265279585548199909383168358934626303861059
      Line 81, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 112631228 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 112639244 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 112639244 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 2/5
        UVM_INFO @ 112641645 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2