AES/MASKED Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: `9464f06a4d`

Branch: dj-sw-nightly

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	29.000s	121.840us	1	1	100.00
V1	smoke	aes_smoke	27.000s	68.478us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	52.557us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	67.191us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	729.130us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	159.279us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	92.266us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	67.191us	20	20	100.00
		aes_csr_aliasing	7.000s	159.279us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	27.000s	68.478us	50	50	100.00
		aes_config_error	27.000s	131.505us	50	50	100.00
		aes_stress	27.000s	69.382us	50	50	100.00
V2	key_length	aes_smoke	27.000s	68.478us	50	50	100.00
		aes_config_error	27.000s	131.505us	50	50	100.00
		aes_stress	27.000s	69.382us	50	50	100.00
V2	back2back	aes_stress	27.000s	69.382us	50	50	100.00
		aes_b2b	34.000s	657.679us	50	50	100.00
V2	backpressure	aes_stress	27.000s	69.382us	50	50	100.00
V2	multi_message	aes_smoke	27.000s	68.478us	50	50	100.00
		aes_config_error	27.000s	131.505us	50	50	100.00
		aes_stress	27.000s	69.382us	50	50	100.00
		aes_alert_reset	28.000s	140.559us	47	50	94.00
V2	failure_test	aes_man_cfg_err	28.000s	62.887us	50	50	100.00
		aes_config_error	27.000s	131.505us	50	50	100.00
		aes_alert_reset	28.000s	140.559us	47	50	94.00
V2	trigger_clear_test	aes_clear	28.000s	260.906us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	34.000s	950.103us	1	1	100.00
V2	reset_recovery	aes_alert_reset	28.000s	140.559us	47	50	94.00
V2	stress	aes_stress	27.000s	69.382us	50	50	100.00
V2	sideload	aes_stress	27.000s	69.382us	50	50	100.00
		aes_sideload	26.000s	162.932us	50	50	100.00
V2	deinitialization	aes_deinit	29.000s	226.254us	50	50	100.00
V2	stress_all	aes_stress_all	1.067m	2.576ms	5	10	50.00
V2	alert_test	aes_alert_test	7.000s	84.880us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	177.407us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	177.407us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	52.557us	5	5	100.00
		aes_csr_rw	5.000s	67.191us	20	20	100.00
		aes_csr_aliasing	7.000s	159.279us	5	5	100.00
		aes_same_csr_outstanding	6.000s	114.583us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	52.557us	5	5	100.00
		aes_csr_rw	5.000s	67.191us	20	20	100.00
		aes_csr_aliasing	7.000s	159.279us	5	5	100.00
		aes_same_csr_outstanding	6.000s	114.583us	20	20	100.00
V2		TOTAL			493	501	98.40
V2S	reseeding	aes_reseed	25.000s	115.872us	50	50	100.00
V2S	fault_inject	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_cipher_fi	59.000s	10.004ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	186.531us	13	20	65.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	186.531us	13	20	65.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	186.531us	13	20	65.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	186.531us	13	20	65.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	69.042us	11	20	55.00
V2S	tl_intg_err	aes_sec_cm	8.000s	371.449us	5	5	100.00
		aes_tl_intg_err	7.000s	1.045ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	1.045ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	28.000s	140.559us	47	50	94.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	186.531us	13	20	65.00
V2S	sec_cm_main_config_sparse	aes_smoke	27.000s	68.478us	50	50	100.00
		aes_stress	27.000s	69.382us	50	50	100.00
		aes_alert_reset	28.000s	140.559us	47	50	94.00
		aes_core_fi	53.000s	10.006ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	186.531us	13	20	65.00
V2S	sec_cm_aux_config_regwen	aes_readability	27.000s	53.461us	50	50	100.00
		aes_stress	27.000s	69.382us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	27.000s	69.382us	50	50	100.00
		aes_sideload	26.000s	162.932us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	27.000s	53.461us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	27.000s	53.461us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	27.000s	53.461us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	27.000s	53.461us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	27.000s	53.461us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	27.000s	69.382us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	27.000s	69.382us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	23.000s	112.558us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_cipher_fi	59.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	113.748us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	23.000s	112.558us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_cipher_fi	59.000s	10.004ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	10.004ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	23.000s	112.558us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_ctr_fi	6.000s	113.748us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_cipher_fi	59.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	113.748us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	28.000s	140.559us	47	50	94.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_cipher_fi	59.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	113.748us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_cipher_fi	59.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	113.748us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_ctr_fi	6.000s	113.748us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	23.000s	112.558us	48	50	96.00
		aes_control_fi	58.000s	10.003ms	287	300	95.67
		aes_cipher_fi	59.000s	10.004ms	332	350	94.86
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	44.000s	4.352ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1532	1602	95.63

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.61	96.52	99.39	95.58	98.07	97.78	98.95	98.99

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 23 failures:

Test aes_shadow_reg_errors_with_csr_rw has 8 failures.

0.aes_shadow_reg_errors_with_csr_rw.27942047021635434834350745551095677409567477897291571594680387851687699122445
Line 104, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  69041651 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  69041651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_shadow_reg_errors_with_csr_rw.34757338389577203953160953500910234300347519314303109510683528378741497158766
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/3.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  17673799 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  17673799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aes_shadow_reg_errors has 7 failures.

1.aes_shadow_reg_errors.78003920633472381233702672506154925357945304817054258434908721213350869304532
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/1.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  35681696 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  35681696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_shadow_reg_errors.26460372963184883899732544741035350674060085306461249250811813069769254663093
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/5.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  34336534 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  34336534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aes_stress_all has 4 failures.

3.aes_stress_all.70411864373949762683671542885628595287562897379186231512676202855497580169004
Line 33996, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/3.aes_stress_all/latest/run.log

  UVM_FATAL @  90073495 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  90073495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all.2418614478410175043233708345414877836876988874306939145714015487919622497479
Line 26138, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/6.aes_stress_all/latest/run.log

  UVM_FATAL @ 363163990 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 363163990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aes_fi has 2 failures.

16.aes_fi.114115602523951002717852175084630030707923422502548667517551570366523640227719
Line 1498, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/16.aes_fi/latest/run.log

  UVM_FATAL @  12595038 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  12595038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.aes_fi.77984394130512246448929885062285810575929037911622485440275446377490889817074
Line 406, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/49.aes_fi/latest/run.log

  UVM_FATAL @   7185393 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   7185393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 2 failures.

43.aes_alert_reset.1003637610333607754758497142767946306006463927221430346208328444072530466270
Line 1555, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/43.aes_alert_reset/latest/run.log

  UVM_FATAL @  41399753 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  41399753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.aes_alert_reset.29408039516321483930528249982586276973057205815176712956206910630117297811550
Line 665, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/47.aes_alert_reset/latest/run.log

  UVM_FATAL @  22820681 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  22820681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_cipher_fi has 18 failures.
  - 29.aes_cipher_fi.85632848955493023860798015964842514924029512743147526300565317194773334019857
    Line 150, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10033063537 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033063537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 109.aes_cipher_fi.2309678315446438900472933876296638874753977503773573859506858689347537184245
    Line 142, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/109.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011951174 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011951174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
Job timed out after * minutes has 9 failures:
- Test aes_control_fi has 9 failures.
  - 13.aes_control_fi.57116306914965542258441594092772296292302809387281072632254051524830718051787
    Log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 68.aes_control_fi.103561720386845578968952894886720919632751013762525008717171649722891804407518
    Log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.30787297485105047730145069089850310595438392258232664661235137538309254513305
Line 1183, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4351508024 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4351508024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.18259628183529865969051421045267106336785950016505966528960711291019145050798
Line 921, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 592394546 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 592394546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 2.aes_stress_all_with_rand_reset.105171886525541469619914360619367322984119380662435625506510129963079076010029
    Line 473, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 524553562 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 524553562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_stress_all_with_rand_reset.108398212910848319147730217581397289752537476356172178895962081461542360301327
    Line 159, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  29266826 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  29266826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 45.aes_core_fi.28471118791909808319278571123369479490205323820156909078711462028625688146686
    Line 145, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010985083 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010985083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 53.aes_core_fi.98303803715893240573983999234015590652078139157282465557223197031357740792059
    Line 135, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009680833 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009680833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 96.aes_control_fi.18076764976789414042936665953281055974662080652664382469724514112635694426954
    Line 139, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/96.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10031557086 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031557086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 150.aes_control_fi.115504278095588903289173997064999809730894078586325598050203126662778663413548
    Line 136, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/150.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026521035 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026521035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 0.aes_stress_all.13078730682574738291346849085908433870592689165775980394498164481511824611954
    Line 32391, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/0.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 6530594485 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6530594485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:980) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 2.aes_shadow_reg_errors_with_csr_rw.11244054387687032315424585208480737209614056780736895807470647801644933375521
    Line 104, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/2.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 342583462 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 342583462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:891) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.111739268474261072143683462154355317214153645972684613629892422168035058331649
    Line 164, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1383732817 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1383732817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

49.aes_alert_reset.48193932097305510855552231754567306938342347468294472798524741951493145594883
Line 898, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/49.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 16468277 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 16455290 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 16468277 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 16455290 PS)
  UVM_ERROR @  16468277 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 281.aes_control_fi.69335722969504360740489161153659749067042271448837389473413892582998750093337
    Line 141, in log /nightly/runs/scratch/dj-sw-nightly/aes_masked-sim-xcelium/281.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```