AES/UNMASKED Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: `9464f06a4d`

Branch: dj-sw-nightly

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	75.796us	1	1	100.00
V1	smoke	aes_smoke	9.000s	849.802us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	79.885us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	59.100us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	5.805ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	152.488us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	144.464us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	59.100us	20	20	100.00
		aes_csr_aliasing	6.000s	152.488us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	849.802us	50	50	100.00
		aes_config_error	7.000s	825.755us	50	50	100.00
		aes_stress	6.000s	194.151us	50	50	100.00
V2	key_length	aes_smoke	9.000s	849.802us	50	50	100.00
		aes_config_error	7.000s	825.755us	50	50	100.00
		aes_stress	6.000s	194.151us	50	50	100.00
V2	back2back	aes_stress	6.000s	194.151us	50	50	100.00
		aes_b2b	9.000s	154.250us	50	50	100.00
V2	backpressure	aes_stress	6.000s	194.151us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	849.802us	50	50	100.00
		aes_config_error	7.000s	825.755us	50	50	100.00
		aes_stress	6.000s	194.151us	50	50	100.00
		aes_alert_reset	6.000s	159.177us	48	50	96.00
V2	failure_test	aes_man_cfg_err	6.000s	98.757us	50	50	100.00
		aes_config_error	7.000s	825.755us	50	50	100.00
		aes_alert_reset	6.000s	159.177us	48	50	96.00
V2	trigger_clear_test	aes_clear	6.000s	92.782us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	185.373us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	159.177us	48	50	96.00
V2	stress	aes_stress	6.000s	194.151us	50	50	100.00
V2	sideload	aes_stress	6.000s	194.151us	50	50	100.00
		aes_sideload	14.000s	747.432us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	72.046us	50	50	100.00
V2	stress_all	aes_stress_all	21.000s	1.662ms	8	10	80.00
V2	alert_test	aes_alert_test	5.000s	74.443us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	80.862us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	80.862us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	79.885us	5	5	100.00
		aes_csr_rw	5.000s	59.100us	20	20	100.00
		aes_csr_aliasing	6.000s	152.488us	5	5	100.00
		aes_same_csr_outstanding	6.000s	499.453us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	79.885us	5	5	100.00
		aes_csr_rw	5.000s	59.100us	20	20	100.00
		aes_csr_aliasing	6.000s	152.488us	5	5	100.00
		aes_same_csr_outstanding	6.000s	499.453us	20	20	100.00
V2		TOTAL			497	501	99.20
V2S	reseeding	aes_reseed	7.000s	232.016us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_cipher_fi	35.000s	10.003ms	327	350	93.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	120.980us	14	20	70.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	120.980us	14	20	70.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	120.980us	14	20	70.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	120.980us	14	20	70.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	498.927us	13	20	65.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.134ms	5	5	100.00
		aes_tl_intg_err	6.000s	301.031us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	301.031us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	159.177us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	120.980us	14	20	70.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	849.802us	50	50	100.00
		aes_stress	6.000s	194.151us	50	50	100.00
		aes_alert_reset	6.000s	159.177us	48	50	96.00
		aes_core_fi	35.000s	10.003ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	120.980us	14	20	70.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	92.821us	50	50	100.00
		aes_stress	6.000s	194.151us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	194.151us	50	50	100.00
		aes_sideload	14.000s	747.432us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	92.821us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	92.821us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	92.821us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	92.821us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	92.821us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	194.151us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	194.151us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	86.225us	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_cipher_fi	35.000s	10.003ms	327	350	93.43
		aes_ctr_fi	5.000s	71.060us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	86.225us	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_cipher_fi	35.000s	10.003ms	327	350	93.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	35.000s	10.003ms	327	350	93.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	86.225us	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_ctr_fi	5.000s	71.060us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_cipher_fi	35.000s	10.003ms	327	350	93.43
		aes_ctr_fi	5.000s	71.060us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	159.177us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_cipher_fi	35.000s	10.003ms	327	350	93.43
		aes_ctr_fi	5.000s	71.060us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_cipher_fi	35.000s	10.003ms	327	350	93.43
		aes_ctr_fi	5.000s	71.060us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_ctr_fi	5.000s	71.060us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	86.225us	47	50	94.00
		aes_control_fi	37.000s	10.015ms	280	300	93.33
		aes_cipher_fi	35.000s	10.003ms	327	350	93.43
V2S		TOTAL			925	985	93.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	2.283ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1528	1602	95.38

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.58	94.54	98.74	93.37	98.07	91.11	98.84	97.38

Failure Buckets

Job timed out after * minutes has 26 failures:
- Test aes_cipher_fi has 16 failures.
  - 19.aes_cipher_fi.35906687787750808453326621231473630505195229122880039730411480419624203221265
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 20.aes_cipher_fi.67543371739975451879374757748250248077079769356844016782868880760982226074113
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
- Test aes_control_fi has 10 failures.
  - 32.aes_control_fi.42027940004211502457420041891075496519046550177860615820063775730637319584061
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 46.aes_control_fi.7414726490735745403527876983842407182068283573199158759110015451137337185736
    Log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 16 failures:

Test aes_shadow_reg_errors has 6 failures.

7.aes_shadow_reg_errors.96386683844341240310442011577257950470194868493957850358662565602046164264849
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/7.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  12474541 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  12474541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aes_shadow_reg_errors.62521782726027988635506461506886419915041832791925651719409831661623940032758
Line 104, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/9.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  13162433 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  13162433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aes_shadow_reg_errors_with_csr_rw has 5 failures.

7.aes_shadow_reg_errors_with_csr_rw.79172788429489909541262426972987804032117595093263620777239038030363280710284
Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/7.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @   9793402 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   9793402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aes_shadow_reg_errors_with_csr_rw.76980507130152704210458676857591850760027680845674508173847698637791070421476
Line 104, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/11.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  50932727 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  50932727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aes_stress_all has 1 failures.

8.aes_stress_all.84131030393598288037820549538340397036128401931560464069600870277550255493406
Line 99508, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/8.aes_stress_all/latest/run.log

  UVM_FATAL @ 341338675 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 341338675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 2 failures.

23.aes_alert_reset.59700175079539378180811807850157458251311017592582770237275037903927578380614
Line 999, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/23.aes_alert_reset/latest/run.log

  UVM_FATAL @  16140410 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  16140410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.aes_alert_reset.86607716187517617038881336840390400782873064748018096701662730968558596988871
Line 661, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/48.aes_alert_reset/latest/run.log

  UVM_FATAL @   3997712 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   3997712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 2 failures.

38.aes_fi.28050442184793077336803973469830124059322940197414877954649503024273932385457
Line 1617, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/38.aes_fi/latest/run.log

  UVM_FATAL @  20590658 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  20590658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.aes_fi.103455133775489082363478666641717897278943333241395520890474147722652117993924
Line 2259, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/46.aes_fi/latest/run.log

  UVM_FATAL @  10384847 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  10384847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 12.aes_control_fi.72940584782189070262106117287738537018259565913137973130799847288566681340022
    Line 137, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014564997 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014564997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.aes_control_fi.24149137747101897303383508285047454391761201226899092754688958177718470561127
    Line 148, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014626592 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014626592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 60.aes_cipher_fi.51491479924730407498524394710701581236821825802826838145709255108092864777260
    Line 136, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002527274 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002527274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 78.aes_cipher_fi.73336267536503253825622585904547304759486805757320388589963325885439777911552
    Line 144, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014227034 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014227034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.20654285396169868736820488254396931823241757399518892017515678094137790596816
Line 624, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1695002315 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1695002315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.97687755299848753051354917357561459242554880793703772548830017115117027116109
Line 224, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 627539774 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 627539774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.30024318380355400144240369088769275867525700567694179820634788194686014387568
    Line 176, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 256155312 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 256155312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.17712791082408181421705776333211775512348903971913280141936629690353018254833
    Line 342, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 719329031 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 719329031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:980) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 2 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 2 failures.
  - 0.aes_shadow_reg_errors_with_csr_rw.23369831559468479192561257057472742533623932546614142855193819950515598072975
    Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 132807346 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 132807346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_shadow_reg_errors_with_csr_rw.17881214065508805325975815542634049070836658600540847967280315625873606484832
    Line 103, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/9.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 148851793 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 148851793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
- Test aes_stress_all has 1 failures.
  - 1.aes_stress_all.109472822706803427796824023969025973625629632500104458285215756146778766320559
    Line 2536, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/1.aes_stress_all/latest/run.log
```
  UVM_ERROR @ 300327804 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 300327804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.32137803690134490272058040967954326820540234050119050530577420618338665384712
    Line 292, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 422557878 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 422557878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.63806465656328524177692887931443345476370621516153701178682690672138524547058
    Line 191, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  24021297 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  24021297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 32.aes_fi.51000021293583278180911370820783719754194940413937921054787577456670945169191
    Line 5610, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/32.aes_fi/latest/run.log
```
  UVM_FATAL @ 226223276 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 226223276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.20899484415515234679370594422626712897596405333900164755918842959188094034330
    Line 142, in log /nightly/runs/scratch/dj-sw-nightly/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002637577 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002637577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```